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Questions tagged [virtex]

Virtex is a series of FPGAs produced by Xilinx

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ChipScope Error - Did not find trigger mark in buffer

Has anybody mentioned data errors, trigger error or upload errors in ChipScope? I'm using ChipScope (from ISE 14.7) with the IP core flow. So I created 15 different ICON IP cores as ngc files and wrapped them all in a VHDL module. This module…
Paebbels
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How can I use 5x5filter (Xilinx block), it keeps telling me there is an error in the counter?

I'm trying to apply edge filter to an image using Xilinx blocks, I used 5x5 buffer then I connected the 5x5filter to it. But it keeps telling me: Illegal Period, This blocks attempts to set period that is a non-integer multiple of the system rate …
Mohammad Algassim
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Creating a single ended clock from differential on board clocks on VC709 fpga board

I am trying to use on- board differential clocks for my verilog code. Below are the snippets of my verilog and constraint files. Even though the code synthesizes well, I am not able to see the LED change on board. Can somebody tell me what I am…
Saloni Raina
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Timing constraint of DCM output is not met

I have a DCM in my design clocked at 100MHz: COMPONENT DCM_100 PORT( CLKIN_IN : IN std_logic;--100MHz RST_IN : IN std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLKOUT0_OUT : OUT std_logic; --divided by 1 CLKOUT1_OUT : OUT std_logic; --divided by…
Sajjad
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Opaque platgen failure in Xilinx EDK

This is running on: Ubuntu 64 LTS Xilinx Platform Studio 14.7 (lin64) I'm trying to run the microblaze_demo project included with the Virtex 5 board provided by PLDkit, but I'm getting a very unhelpful error. short error log Running XST synthesis…
Alex Raster
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what is syntax in ucf file for IOBDELAY for virtex 5?

# Sets the attributes to an input differential pin pair (din) NET LOC= | IOSTANDARD= |IOBDELAY= | DIFF_TERM=; NET LOC= | IOSTANDARD= | IOBDELAY= |…
atnd9
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how to connect LVDS signals coming from test equipment to fpga virtex 5 when the design has only input signal Din ?

I would provide din+ to A1 and din- to A2, on pin connector on PM2 module, connecting to FPGA, but I have only 1 input port "din" in top level vhdl design module connected to AG7 pin on FPGA. How to go about connection in UCF file ? PM2 Pin - A1,…
atnd9
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how to generate high frequency (64 MHz) clock from very low frequency (1.33MHz) clock source in Xilinx Virtex-6

I need to generate an internal 64 MHz clock signal in a Virtex-6 Xilinx FPGA based on a 1.333 MHz input clock pin. If I use the Clock Generator wizard in the ISE tool, it only allows input clock frequencies down to 10 MHz. How can a 1.33 MHz clock…
Torben Jacobsen
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interfacing VGA with Virtex-5 FPGA board

I need to interface VGA screen to Virtex-5 FPGA board in order to display an image. I know how to interface VGA with Spartan-3E starter board. But I have no idea how to do it with Virtex-5.
Utkarsh Jain
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How to vary the supply voltage for Xilinx Virtex-5 FPGA ML501, ML506, and ML510 boards?

I'm trying to do an experiment to see how different supply voltages affect the frequency of ring oscillator and the reliability of SRAM cells. I have access to a couple of Xilinx Virtex-5 boards, namely, ML501, ML506, and ML510. I have tried to…
abc
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How to use the memory of the Xilinx-FPGA Virtex5/7 as a memory mapped into the x86-CPU's address space?

Is it possible to use the memory of the Xilinx-FPGA Virtex5/7 as a memory mapped into the virtual and/or physical address space of the Intel x86_64-CPU's memory and how to do it? As maximum, I need to use unified single address space with having of…
Alex
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How to interface a vga monitor to fpga using verilog?

I am using virtex - 5 fpga board and i am new in working with fpga board please suggest me any kind of material to have example codes for example to display a simple name on the monitor..
Red1
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VHDL Verilog Integer Arrays Ports

I am working on a project for the FPGA implementation of the Breakout Game. In this game, we have to break the bricks using a ball and a paddle. Some bricks may break on multiple contacts with the ball. For this, I am using an integer array to…
akhiljain
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Sasebo GII virtex5 fpga configuration

I am working with Sasebo GII board that has two FPGAs on it: Xilinx Spartan and Xilinx Virtex5 (and the board has several separate JTAG interfaces for configuration of fpgas). I am useing ISE 14.4 under Linux and I have some troubles to configure…
CorsairNV
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Writing i/o constraints for virtex 5

Guys I am working on virtex 5 board and I don't know how to write I/O constraints. Can someone suggest some good tutorials with basic about writing constraints. I have tried Xilinx Constraint Guide, its too lengthy and hard to be understood by a…
Akash
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