Writing i/o constraints for virtex 5

Question

Guys I am working on virtex 5 board and I don't know how to write I/O constraints. Can someone suggest some good tutorials with basic about writing constraints. I have tried Xilinx Constraint Guide, its too lengthy and hard to be understood by a beginner. I want something more simple and too the point. Thanks in advance

Answer 1

Basic minimum you could do is the following:

NET "INPUT_A" LOC = "E13";

Where INPUT_A is the top level net name and E13 is the output pin you want that net to be assigned to. (NET = net name, LOC = pin number assignment)

Going a bit farther you could assign the IOSTANDARD which is the type of signalling, i.e. LVCMOS, LVDS, and so forth. If you leave it blank, I believe it defaults to LVCMOSxx, where xx is the voltage of that particular IO bank.

NET "INPUT_A" LOC = "E13" IOSTANDARD = "LVCMOS33";

There are more constraints such as assigning PERIOD to a net, more specifically a clock net, to allow the tool to do timing closure.