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I need to generate an internal 64 MHz clock signal in a Virtex-6 Xilinx FPGA based on a 1.333 MHz input clock pin. If I use the Clock Generator wizard in the ISE tool, it only allows input clock frequencies down to 10 MHz. How can a 1.33 MHz clock input be used as clock source for a MMCM?

Torben Jacobsen
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  • As your already found, your Fin is below Fmin of the MMCM. You could try to operate the MMCM at these frequencies, but you are out of specs. So garantied output quality is not asured. You'll also need to set the parameters by hand or use 13.33 MHz for the wizard. All parameters (multipliers, dividers) are relative to Fin. – Paebbels Jan 20 '16 at 01:53
  • Do you have access to any faster clocks? Is there an internal (probably high jitter) clock built into the Virtex-6? I know some FPGAs offer this... it might not be great, usually these are subject to high jitter and large drift. – Russell Jan 21 '16 at 17:47
  • We are trying to emulate an ASIC design that only has a 1.33 MHz input clock, and we would like to use the same approach for the FPGA, but it seems not to be possible - and several of you have also stated. I have tried to define the input clock as 13.33 MHz for the wizard, but it wont synthesize unless I also cheat with the timing constraints, so that is a no go. – Torben Jacobsen Jan 23 '16 at 13:19

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