Creating a single ended clock from differential on board clocks on VC709 fpga board

Question

I am trying to use on- board differential clocks for my verilog code. Below are the snippets of my verilog and constraint files. Even though the code synthesizes well, I am not able to see the LED change on board. Can somebody tell me what I am missing here?

Verilog:

module leds(
    input DIFF_SYS_P,
    input DIFF_SYS_N,
    output reg [7:0] leds=8'd0,
    output clk
    );

    reg [31:0] count =0;
    wire clk;



    IBUFGDS #(
    .DIFF_TERM("FALSE"),
    .IBUF_LOW_PWR("TRUE"),
    .IOSTANDARD("DEFAULT")
    ) IBUFGDS_inst (
       .O(clk),
        .I(DIFF_SYS_P),
        .IB(DIFF_SYS_N)
        );


    always@(posedge clk) begin 
      if(count ==10) begin
        leds <= 8'b10101010;
        count <=count +1;
       end

       else begin
       count<=count +1; 
     end
  end
endmodule

Constraints (xdc):

set_property PACKAGE_PIN G18 [get_ports DIFF_SYS_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DIFF_SYS_N]
set_property PACKAGE_PIN H19 [get_ports DIFF_SYS_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DIFF_SYS_P]
set_property PACKAGE_PIN AM39 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[0]}]
set_property PACKAGE_PIN AN39 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[1]}]
set_property PACKAGE_PIN AR37 [get_ports {leds[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[2]}]
set_property PACKAGE_PIN AT37 [get_ports {leds[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[3]}]
set_property PACKAGE_PIN AR35 [get_ports {leds[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[4]}]
set_property PACKAGE_PIN AP41 [get_ports {leds[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[5]}]
set_property PACKAGE_PIN AP42 [get_ports {leds[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[6]}]
set_property PACKAGE_PIN AU39 [get_ports {leds[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[7]}]
create_clock -period 5.000 -name DIFF_SYS_P -waveform {0.000 2.500} [get_ports DIFF_SYS_P]**

Possible duplicate of [Using single ended port in logic expecting diff-pair?](https://stackoverflow.com/questions/32745174/using-single-ended-port-in-logic-expecting-diff-pair) — Patrick Roberts, May 08 '18 at 21:31
By the way, I would remove the `count <= count + 1;` inside the `if` statement and unwrap the second occurrence from the `else` block so it reads `if ... end count <= count + 1;` since it will happen regardless of the conditions. Makes your code more DRY. — Patrick Roberts, May 08 '18 at 21:33
You can run a simulation with the IBUFGDS. There is a library with all Xilinx components. That should tell you what is going wrong. — Oldfart, May 08 '18 at 21:43
First simulate your code. Do you want your led to toggle? You don't reset `count` when reaching `10`, and also don't reset the leds and they remain constant. Simulate first, synthesize later. — Oron Port, May 09 '18 at 12:52
Additionally, you would need a much larger count threshold to notice led change. The frequency is `200MHz`. You count until 10 (from 0), so the effective frequency would be ~`20MHz`. You cannot notice. Change the count threshold to generate a proper toggling rate. — Oron Port, May 09 '18 at 12:55
Did your LEDS stay off? Or did you see them turn on? Also, the constraints you posted lacked a location for the output clk pin. — Jamey Hicks, May 09 '18 at 16:40

score 0 · Answer 1 · answered Jun 06 '18 at 09:04

First, you may want to follow up your IBUFGDS with an IBUFG to actually get the clock onto the global clock network. After that, you're going to want to divide by a LOT more than 10 in order to see any flashing. I would suggest counting to 100 million, resetting the counter, and toggling the LEDs instead of just setting them.

Creating a single ended clock from differential on board clocks on VC709 fpga board

1 Answers1