Make a simple circuit to dissipate power in VHDL

Question

I'm looking for ideas on something simple to write that I can use to measure power. I just need it to make sure that my power measurement is working. I'm using Xilinx ISE 14.1 on a Virtex-6. I'd like a simple circuit to write and to synthesize.

So far I tried a 1K bit counter, but that wasn't really noticeable. I tried a 9K bit counter, but ISE had trouble synthesizing it (I let it run for an hour before killing it). Now I am trying to implement large BRAMs and keeping them permanently enabled.

I need a way to restrict large vectors from getting optimized so I'd like to xor all the bits together and feed the single bit output to an LED. Is there an easy way to do this for very large vectors?

In case you're curious, adding bits to your counter should not have had an appreciable impact on power consumption. Bits that don't change state don't dissipate much power, and the n^th bit in your counter only flips every 2^n clocks. There's a lot of literature on power dissipation in ICs, and FPGAs in particular, but the most generic model is P = aCV^2f where P is the power, C is the gate capacitance, V is the voltage, and f is the frequency. The "a" term is an activity factor between 0 and 1 that defines how often bits flip. — Graeme, Aug 20 '12 at 22:47

score 2 · Answer 1 · answered Aug 17 '12 at 10:16

2

In VHDL 2008 you can xor a bunch of bits like this:

signal wide : std_logic_vector(1000 downto 0);
signal narrow : std_logic;

narrow <= xor wide;

Not sure if ISE supports that.

You could use a function like:

function xor_vector(i:std_logic_vector) returns std_logic is
  variable ret:std_logic:=i(i'low);
begin
  for c in i'low+1 to i'high loop
    ret := ret xor i(c);
  end loop;
  return ret;
end function;

(Untested, just typed straight in - might need syntax tweaks!)

For power dissipation, you might try feeding an alternating '1' and '0' pattern into a shift register rather than a counter - then all the bits will change every cycle. Put a reset on the shift register to ensure that the tools don't infer SRL16 to be more efficient.

answered Aug 17 '12 at 10:16

Martin Thompson

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To add to Martin's suggestion, use a for ... generate loop to create many smaller xor type combinations. Then have one place where you combine together all of the outputs of the for loop and tie to an LED. You will be less likely to run into map/placement issues if you can break your design down into smaller pieces. Also, remember to use a combination of synchronous (FF) and async (LUT) elements. – Josh Aug 17 '12 at 10:47
@josh: Using a for..generate vs a function vs the `xor` function on a vector will produce exactly the same results. The synthesiser will see the logic just the same and optimise it just the same. If it doesn't (IMHO) it's a bug – Martin Thompson Aug 17 '12 at 11:13
Yes, agreed. They will likely go together. Use the function you show inside a for-generate. – Josh Aug 17 '12 at 11:19
@Josh - no need for a generate - just pass in the whole 1000-bit vector (or however big it is) and let the tools do the rest. – Martin Thompson Aug 17 '12 at 11:47
@Josh: Can you explain why I should have a combination of sync and async elements? – Stuart Aug 17 '12 at 18:04
@Stuart The async portion of your design will be the LUTs/logic elements implemented as xor. The sync portion will be registered xor result. If you generate a giant asynchronous xor straight to LED, then a good portion of the chip, the synchronous elements (flip flops), will not be exercised. Place and route will bypass these elements. By driving flip flops with output(s) of xor, then these elements will also be used in addition to LUTs (which implement the xor). – Josh Aug 17 '12 at 19:54

score 0 · Accepted Answer · answered Aug 21 '12 at 00:29

Here is what I came up with. I feel like it gives a good compromise for simple code and quick compile times. It is a shifter, with every other bit high, therefore every FF should be switching every clock cycle (after it has been setup). The signal could be initialized at the beginning if desired, but it shouldn't take more than a second or two, depending on your clock, to reach equilibrium. I used an led as an output to prevent optimizing of the circuit.

architecture Behavioral of top is
signal shifter : std_logic_vector(<insert size> downto 0) := (others => '0');
begin    
        process(clk)
    begin
        if(clk'event and clk = '1')then
            shift_bit <= not shift_bit;
                shifter <= shift_bit & shifter(shifter'high downto 1);
        end if;
    end process;

led <= shifter(0);
end Behavioral;

This should be much easier to synthesize than a large XOR gate because each shifter slice should only need to have fanout and fanin of 1. — Stuart, Aug 21 '12 at 00:30

Make a simple circuit to dissipate power in VHDL

2 Answers2