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I am using Virtex-7 Evaluation board which has 200Mhz clock. My design has a critical path less than 4ns. I am trying to use clock wizard IP to generate 120MHZ clock from the input clock of 200MHz. However, I faced with failing timing after implementation. I look through timing summary and it seems that the critical path does not change while I have a large negative slack. I am wondering why this happen? Why there is large negative slack while the critical path remain the same?

Elnaz
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  • How have you calculated the critical path ans WNS before you inserted the MMCM? Please upload the necessary report lines from the timing report. 200 MHz has a 5 ns period. Why does your 4 ns path not fit? 4 ns <-> 250 MHz. – Paebbels Jan 05 '18 at 20:46
  • I added the Clock constraint on my XDC file to calculate critical path. My critical path is less than 8ns. When I define the clock constraint to 8ns there is no timing problem. I faced with timing problem when I add clock wizard IP with clock frequency of 125MHz or even 120MHz. – Elnaz Jan 06 '18 at 20:37
  • I assume, your circuit was not fully constrained befor you used the wizzard. Not it's constrained and reports the failing paths. Not, static timing analysis can only calculate timings for specified constraints. If you haven't constrained every clock, STA can not calculate the timings. – Paebbels Jan 06 '18 at 22:27

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