5
 module median_five(out1,a[0],a[1],a[2],a[3],a[4],en,clka);             
    input [7:0] a[0:4];              
    output out1;              
    endmodule

**It is giving error. 

 module median_five(out1,a,b,c,d,e,en,clka);             
        input [7:0] a,b,c,d,e;              
        output out1;              
        endmodule

**It is right.

But I want input a,b,c,d,e in array like : 

array[0]<=a;            
array[1]<=b;               
array[2]<=c;             
array[3]<=d;            
array[4]<=e;
sharvil111
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B.R
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1 Answers1

11

Verilog does not support two dimensional arrays as ports of modules. This feature is supported by SystemVerilog only.

In the first snippet, you are passing two dimensional array a as input, which is not supported. In the latter case, a single dimensional vector is passed to the module which works fine.

It is not clear what you want to do with array. Here are some options. You can declare two dimensional array inside the module itself. Something like follows:

module median_five(out1,a,b,c,d,e,en,clka);
input [7:0] a,b,c,d,e;
output out1;

ref [7:0] array [5]; // array local to module

//always @(posedge clka)  // use non blocking assignments
always @(*)              // use blocking assignments
begin
// .. Some stuff
array[0]=a;            
array[1]=b;               
array[2]=c;             
array[3]=d;            
array[4]=e;     
//..       
end

//.. some other stuff

endmodule

Another thing you can do is to flatten the array and pass it as inputs. Here, I have flattened each of 8 bit input (a,b,c etc. each) into a single vector (in) and assigned each individual element of array accordingly.

module top (in, out);
  input   [31:0] in; // flattened array as input
  output  [31:0] out;

  wire     [7:0] array [0:3]; // local array

  assign {array[3],array[2],array[1],array[0]} = in;
  //... some operations/procedural blocks etc.
  assign out = {array[3],array[2],array[1],array[0]};
endmodule

Refer to Inputs as two dimensional array link for a similar question. There is a similar blog post too.

sharvil111
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  • I wanted to do the sorting. That's y I needed elements in an array . Thanks – B.R Apr 02 '16 at 08:05
  • reg [3:0] r=1; r<= r+ ((e>a) + (e>b)+ (e>c) +(e>d)); its giving unknown value in output. But when i wrote reg [3:0] r=1; r<= ((e>a) + (e>b)+ (e>c) +(e>d)); Its giving output accordingly but i wanted to the first expression r<= r+ ((e>a) + (e>b)+ (e>c) +(e>d)); needed to simulate correctly. Please give hint. – B.R Apr 02 '16 at 08:07
  • Using the first equation, you might be creating a [combinational loop](http://fpga-hdl.blogspot.in/2012/07/test.html) and thence output might not be as per requirement. One method of avoidance of combinational loop is described [here](http://electronics.stackexchange.com/questions/121161/understanding-combinational-feedback-loops). I have created a sample at [EDAPlayground](http://www.edaplayground.com/x/eke). – sharvil111 Apr 02 '16 at 08:47