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I have a DUT that can take packets from all 4 identical interfaces (A, B, C, D) Packets from one port can go to either one of the output ports (1,2,3,4). Example: Packets from A can go onto 1, 2, 3 or 4. Packets from port B can go to 1, 2, 3 or 4 and so on. Packets coming on the same port are in order but packets can be serviced in any order between A, B, C, D (no order is maintained between ports since all 4 interfaces can be active at the same time sending packets).

How do I verify such a DUT? What scoreboard data structure to use? I need to treat the DUT as a black box for I do not know how does the DUT decide which port to send the packets on. I have an uvm agent on each of the 4 interfaces A, B, C and D. A virtual sequence controls the sequences on all 4 agents.

Any inputs? Thanks in advance.

Verif_engg
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    Your question is too broad. I would use `uvm_tlm_analysis_fifo` in my scoreboard to collect packets and process them as required. – noobuntu Sep 13 '17 at 18:21

1 Answers1

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Your question is very broad and opinion based. You can only verify based on the requirements that are given to you. A packet that comes in has to come out intact. If there are no requirements about which ports they come through, then it should not matter to your testbench. There must be some other requirements that deal with throughput that you have not mentioned.

In the simplest situation, you need to make all your packets unique with a global packet ID so that you can send them to a common scoreboard, and at the end of the test, match up all the received packets with the sent packets. An associative array with the packed ID works well for this.

dave_59
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