A test bench or testing workbench is an (often virtual) environment used to verify the correctness or soundness of a design or model, for example, that of a software product.
Questions tagged [test-bench]
292 questions
1
vote
2 answers
I get a warning about $readmemh: Too many words in the file
Here is how I define the rom module
module rom(
input wire [31:0] inst_addr_i,
output reg [31:0] inst_o
);
reg [31:0] rom_mem[0:100];
always@(*) begin
inst_o = rom_mem[inst_addr_i>>2];
end
endmodule
Here…
shikyeeee
- 35
- 6
1
vote
1 answer
Retrieving Data from Register File (Unpacked Array)
I try to write a register file for updating and retrieving data from it. Here is my code
module RegisterFile(input logic clk
,input logic M_we // M_we is write enabled
,input logic M_re…
Lapaaci
- 119
- 7
1
vote
1 answer
Getting output of convolutional PE as XXX instead of a number?
`timescale 1ns / 1ps
// Description: This device performs convolution operation with a 3x3 kernel.
//////////////////////////////////////////////////////////////////////////////////
module PE#(
bit_width = 3,
out_bit_width = 9
…
user17408585
- 11
- 1
1
vote
2 answers
Why am I getting the error : part select cannot be applied to scalar in my testbench?
I have designed a multiplier circuit that has two 32-b inputs, that would be split into two 16-b values and multiplied separately after which the results will be added together. Here is a part of the logic:
parameter WordLen1 = 32, WordLen2 = 16;…
priscilla
- 11
- 6
1
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1 answer
Why is the direction in port mappings from the design to the test-bench and not vice versa?
When testing with a testbench in VHDL we map the I/O from the design we are testing to the I/O of the test bench.
For me, it would make sense to give the input of our design some generated values from the testbench and then observe the output from…
stht55
- 390
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1
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3 answers
$fclose placement in testbench
I want to use $fmonitor so that an output value is written to a file every time the value changes.
When I place $fclose inside the initial begin block, there are no errors. However, unsurprisingly, the output file is empty.
When I place $fclose…
Rahel Miz
- 159
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1
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1 answer
No response from uut in testbench
I am not getting any response from the uut in the testbench. The module exp2_up_down_counter works ok without testbench, but gives output as xxxx when instantiated in the testbench.
Here is the main module of the up-down counter:
`timescale…
Chaitanya Chhichhia
- 13
- 4
1
vote
2 answers
No output data in sinc3 filter simulation
I have the following code for sinc3 digital filter in verilog:-
`timescale 1ns / 1ps
module dec256sinc24b
(input mclk1, /* used to clk filter */
input reset, /* used to reset filter */
input mdata1, /* input data to be filtered */
output reg…
Pressing_Keys_24_7
- 1,755
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- 33
1
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1 answer
How can I use display or monitor in verilog to check a register
I have 2 Modules. One is Register_File_Rf which is a file of 32 Registers I have created. I want to be able to see what every single register is storing.
Can I do this with $display or $monitor somehow?
Where these should be? In actual code or in…
Xhulio Xhelilai
- 45
- 7
1
vote
1 answer
Testing multiple configurations of parameterizable modules in a Verilog testbench
Say I have a Verilog module that's parameterizable like the below example:
// Crunches numbers using lots of parallel cores
module number_cruncher
#(parameter NUMBER_OF_PARALLEL_CORES = 4)
(input clock, ..., input [31:0] data, ... etc);
…
John M
- 1,484
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1
vote
2 answers
I am trying use the output of a 16-bit encoder as to give input to the register (PIPO)
I am trying use the output of a 16-bit encoder as to give input to the register(PIPO).
The 16-bit encoder will give 4-bit binary output; these 4-bit binary output will be given as input to the register.
`timescale 1ps/1ps
module encoder16to4…
Sobebar Ali
- 59
- 5
1
vote
1 answer
Capturing the right posedge clock in Quartus waveform
I am using Quartus Prime Lite 19.1.0.
module memory_address_register1 #(
parameter ADDR_WIDTH = 4
)(
input clk, rst, load,
input [ADDR_WIDTH-1:0] add_in,
output reg …
Blaco
- 109
- 8
1
vote
1 answer
Program Counter not incrementing
I am attempting to create a program counter for a RISC processor, but I am unsure why the test bench isn't working as expected. There might be something wrong with the way the test bench is written, but I can't seem to find it. In the simulation of…
Bram
- 17
- 2
1
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1 answer
Unexpected warning in Verilog simulation for port size
I couldn't figure out why the simulator gives the warning and why the circuit does not work properly.
This is the Verilog code:
`timescale 1ns/1ns
module circuitIVEightBitAssign(input [7:0]a,flag,output [7:0]b);
assign #(143) b = flag ? ~a :…
Ali Eftekhari
- 23
- 3
1
vote
2 answers
Not seeing a clock cycle delay in Vivado simulation during a register/flipflop assignment
I am trying to generate a pulse from a signal ext_sample_clk. My design currently has 2 clock signals, clk and ext_sample_clk, which I am generating through a testbench. The following is my simplified code. Besides this, I also have the clk and…
user2532296
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