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I have in VHDL a code segment which makes me unsure if it's right: a and b are std_logic_vectors. c1 and c0 are std_logic. Is this correct written? Especially the part "c1 = '1' and c0 = '0'" struggels with me.

if unsigned(a) > unsigned(b) then
    assert(c1 = '1' and c0 = '0')

Edit: Here is a bigger code segment:

    signal a: std_logic_vector(3 downto 0);
    signal b: std_logic_vector(3 downto 0);
    signal c1: std_logic;
    signal c0: std_logic;

    begin
    TEST: forBitComperator port map(a, b, c1, c0);
      process
      begin
        for i in 0 to 2**4-1 loop
            for k in 0 to 2**4-1 loop

                wait for 0 ns;

                a <= conv_std_logic_vector(i, 4);
                b <= conv_std_logic_vector(k, 4);

                if i > k then
                  assert c1 = '1' and c0 = '0'
                  report "error ";
               end if;
        end loop;
    end loop;
    wait;
  end process;
end;
bilaljo
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  • The assertion statement lacking either a report or severity clause should be terminated with a semicolon (IEEE Std 1076-2008 10.3 Assertion statement "An assertion statement checks that a specified condition is true and reports an error if it is not."). The assertion statement is otherwise syntactically correct, there's a default error message. A specific question concerning usage semantics could benefit from a [mcve] which also demonstrates object declarations, c1 and c0 are apparently of some character enumerated type. The enclosing if statement (10.8) is not syntactically complete. –  Dec 29 '19 at 16:07
  • The parentheses are superfluous in the assertion statement snippet. An expression enclosed in parentheses is only valid if it is also valid without the parentheses, the shown expression only contains one logical operator, requiring no parentheses to establish precedence (9.1, 9.2.1). –  Dec 29 '19 at 16:15
  • You're right thank you. – bilaljo Dec 29 '19 at 17:56
  • I highly recommend that you keep all the `end` statements. Removing them just creates unnecessary confusion. – Harry Dec 29 '19 at 19:50
  • Sorry, I added them (I've saw I deleted the wait statement). – bilaljo Dec 29 '19 at 21:36

1 Answers1

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The parts you were unsure about are correct. c0, c1, '0' and '1' are all std_logic, so it is correct to compare them in this way. (In VHDL = is the equality comparison operator. It doesn't perform an assignment, like in many software programming languages). The result of each comparison is a boolean (true or false) so can be used with an assert statement.

The only part that I think is really wrong is that you must end your if with an end if. It is usually also recommended that whenever you use assert, you report an error message and set a severity (e.g. note, warning, error or failure, depending on how serious the error is). Of course, it must also be terminated with ;.

Therefore:

if unsigned(a) > unsigned(b) then
    assert c1 = '1' and c0 = '0' report "<Error message>" severity warning;
end if;
Harry
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  • Thank you for the answer. Oh, you're right, I missed to copy "end if" in my post. Hm it's still very strange because the assert generate in my testbench only errors (if I test those cases manually they are correctly). – bilaljo Dec 29 '19 at 16:27
  • Do you mean it reports syntax errors (at compile time) or assertion errors (at run time)? I think it is likely that your code is correct, it is reporting errors correctly, but you don't understand why. You will need to give much more specific details if you want help with that. – Harry Dec 29 '19 at 16:57
  • *Hm it's still very strange because the assert generate in my testbench only errors...* The condition `c1 = '1' and c0 = '0'` would evaluate to FALSE causing the assertion if either c1 /= '1' or c0 /= '0' (DeMorgan's theorem). None of your three questions has provided any clear indication what c1 and c0 represent nor have you demonstrated the original Python code you're trying to produce a VHDL equivalent of unsuccessfully. –  Dec 29 '19 at 17:11
  • I meant assertion errors. c1 and c0 representing bits: c1=1 and c0=0 for example means a > b. c1=0 and c0=1 a – bilaljo Dec 29 '19 at 17:51
  • When you check the results manually, how do you do this? Do you just look at the waveform plots in your simulator? Do they look identical? Do you expand delta cycles in the waveform plots? Testing combinational logic can be very confusing if you don't understand the concept of delta cycles. I suspect this may be your problem. One way to check this is to simply register `i`, `k`, `c0` and `c1` (so they're all synchronous) and see if the errors go away. However, we're now getting very far from your original question, which was about VHDL syntax. – Harry Dec 29 '19 at 20:02
  • By the way, I found my mistake: I used "wait for 0 ns" but I should used "wait for 1 ns". Everything is working now. Thanks for help. – bilaljo Dec 30 '19 at 07:58