My testbench always shows X as the outputs

Question

I'm not able to identify the bug, but all the code seems logically and syntactically right. The value of sum and carry in the testbench are always X. There are two modules, one for an 8bit adder and another for a 16bit adder :

module adder_8(in1 , in2 , cin , sum , carry);

input [7:0] in1 , in2;
input cin;
output reg [7:0] sum;
output reg carry;

always @(in1 or in2) begin
    {carry , sum} = in1 + in2 + cin;
end
endmodule

module adder_16(input_a , input_b , c , summation , cout);

input [15:0] input_a , input_b;
input c;
output [15:0] summation;
output cout;

wire t1;

adder_8 inst1 (input_a[7:0] , input_b[7:0] , c , summation[7:0] , t1);
adder_8 inst2 (input_a[15:8] , input_b[15:8] , t1 , summation[15:8] , cout);

endmodule

The test bench file is :

module testbench;

reg [15:0] a,b;

wire [15:0] sum;
wire carry;

parameter zero = 1'b0;

adder_16 ex(a , b , zero , sum , carry);

initial begin

    $monitor($time," A = %d , B = %d sum = %d carry = %b", a , b , sum , carry);

    #10 a = 16'd 100; b = 16'd 100;

    #10 a = 16'd 50; b = 16'd 20;

    #20 $finish;

end
endmodule

I would really appreciate some help.

Answer 1

cin is missing from the sensitivity list in always @(in1 or in2). It should be always @(in1 or in2 or cin) to be complement with the 1995 version of the standard. The 2001 version of the standard improved it to always @* (or the synonymous always @(*) for an automatic sensitivity list.

If you are targeting for SystemVerilog, use always_comb (no @ or signal list). This will add an extra compile time check to make sure a the logic is not assigned in another always block which would make the code non-synthesizer.