Questions tagged [system-verilog-dpi]

Direct Programming Interface (DPI) from SystemVerilog. This interface allows direct communication between SystemVerilog simulation and foreign programming languages.

Direct Programming Interface (DPI) from system-verilog. This interface allows direct communication between SystemVerilog simulation and foreign programming languages. Different programming languages can be used to intact with SystemVerilog; however, the SystemVerilog LRM (IEEE Std 1800-2017) only defines the C programming language as a foreign language layer.

Full details can be found in IEEE Std 1800-2017 § 35 Direct programming interface

55 questions

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1 answer

How to Pass array from C to SV using SV-DPI?

My objective is to pass an array from C to SV and print the array contents in SV, I have tried the following C program of converting some text file(data_file.txt) (given full source in the link below) to an array and trying to read back the array by…

c system-verilog system-verilog-dpi

asked Jul 28 '17 at 15:43

Emman

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1 answer

Creating C++ testbench to drive a Verilog DUT

I'm trying to understand how to create a C++ testbench to drive stimulus to a DUT in Verilog. Let's say I have a simple scenario: // Testbench Top. module tb_top(); import "DPI-C" function void wait_for_input_ready(); initial …

c++ verilog system-verilog system-verilog-dpi

asked Oct 19 '15 at 06:40

sundar

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2 answers

Can I get a call graph of C routines which are called via a DPI call from a system verilog testbench

I am working on a verification project. Certain testbench components are written in c which are called via DPI, the c routines are extensive and i am having difficult time in figuring out which routine is called by whom. A pure C program may be I…

c system-verilog system-verilog-dpi

asked Apr 13 '15 at 10:56

Gautam

-1

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1 answer

How to connect 2 ports(input) to same wire in verilog

Instantiate the following module connecting ports by name. The output of the module should be connected to wire S, port B should connect to wire T, and port C should also connect to wire T. my_module(output A, input B, input C); How can I write…

verilog xilinx-ise system-verilog-dpi

asked Feb 27 '20 at 18:59

Hassaan

-1

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1 answer

Accessing internal modules(tb.dut.a.b) apb interface at top tb level

Is there any way I can connect an apb master vip to internal module inside dut which have apb signals in it . I want to program some registers in this deep inside dut module . I tried to connect an interface and bind it at deep inside module ,…

verilog system system-verilog uvm system-verilog-dpi

asked Jul 27 '19 at 15:36

Verifexplorer

-1

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1 answer

Use define between systemverilog and DPI-C

In systemverilog sv_define.vh `define A_MODULE_ENABLE //`define B_MODULE_ENABLE In C c_define.h #define A_MODULE_ENABLE //#define B_MODULE_ENABLE Since syntax for "define" is different between systemverilog and C. If I want to…

system-verilog-dpi

asked Mar 18 '19 at 08:43

Julung Fan

-1

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1 answer

Accessing a shared memory

I am trying to verify a sMEM design using assertions in systemVerilog however I got a problem I did not Know How to solve it : I am supposed to verify if: On rising edge of CLKA, when BLKA is 1 and RWA is 1, data is read at ADDRA address of…

system-verilog uvm system-verilog-assertions system-verilog-dpi

asked Sep 28 '18 at 08:55

mariam

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1 answer

C to SystemVerilog, My output is incorrect

I am trying to get my system verilog code to work with my c code, but I am getting a strange output. My exp_data_out should be the output of my encoder but it is zzzzxzzzzzxzxzz instead. Can someone tell me why the output is this? C void encoder( …

c system-verilog system-verilog-dpi

asked Oct 31 '15 at 10:10

excode

-2

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1 answer

is there any API to convert "svLogicVecVal *" to "uint_8"?

my input in systemverilog is in bits; but I need it to be in uint8_t. is API or library can do it? FYI, Im trying to verify verilog results with .C using "dpi". system verilog: //import "DPI-C" function int test_encrypt_ecb(); import "DPI-C"…

c verilog system-verilog system-verilog-dpi

asked Jan 21 '23 at 15:30

jeff

-2

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4 answers

error: cannot convert 'bool' to 'svLogic*' in assignment

We are working on the system verilog DPI calls. While compiling the C++ file we are getting the errors like this: error: cannot convert 'bool' to 'svLogic*' in assignment Here svLogic is 4-state variable. The VCS simulator has predefined…

c++ gcc system-verilog modelsim system-verilog-dpi

asked Jun 02 '15 at 05:19

Santhosh Kumar

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