-1

In systemverilog sv_define.vh

`define A_MODULE_ENABLE
//`define B_MODULE_ENABLE

In C c_define.h

#define A_MODULE_ENABLE
//#define B_MODULE_ENABLE

Since syntax for "define" is different between systemverilog and C. If I want to config ENABLE, I have to modify those two files, that would sometimes be troublesome. How can I just define them in a single file and include it ? Thanks a lot.

My imagination: my top.sv and top.c would include the same file: c_sy_define.vh The content would be:

__SV__
    `define A_MODULE_ENABLE
    //`define B_MODULE_ENABLE
__C__
    #define A_MODULE_ENABLE
    //#define B_MODULE_ENABLE

1 Answers1

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Yeap. This will probably work. Never try it though.

#ifndef COMPILE_IN_C
`define A_MODULE_ENABLE
#endif

`ifndef COMPILE_IN_SV
#define A_MODULE_ENABLE
`endif

Wen you compile the header file, make sure you add "-define COMPILE_IN_SV" in ncvlog (say you use Cadence), and add "-DCOMPILE_IN_C" in gcc.

hevangel
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