In systemverilog sv_define.vh
`define A_MODULE_ENABLE
//`define B_MODULE_ENABLE
In C c_define.h
#define A_MODULE_ENABLE
//#define B_MODULE_ENABLE
Since syntax for "define" is different between systemverilog and C. If I want to config ENABLE, I have to modify those two files, that would sometimes be troublesome. How can I just define them in a single file and include it ? Thanks a lot.
My imagination: my top.sv and top.c would include the same file: c_sy_define.vh The content would be:
__SV__
`define A_MODULE_ENABLE
//`define B_MODULE_ENABLE
__C__
#define A_MODULE_ENABLE
//#define B_MODULE_ENABLE