Questions tagged [system-verilog-dpi]

Direct Programming Interface (DPI) from SystemVerilog. This interface allows direct communication between SystemVerilog simulation and foreign programming languages.

Direct Programming Interface (DPI) from system-verilog. This interface allows direct communication between SystemVerilog simulation and foreign programming languages. Different programming languages can be used to intact with SystemVerilog; however, the SystemVerilog LRM (IEEE Std 1800-2017) only defines the C programming language as a foreign language layer.

Full details can be found in IEEE Std 1800-2017 § 35 Direct programming interface

55 questions

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1 answer

Is there DPI-C compatible types for types?

I was attempting to write a struct compatible with DPI-C for Verilog. The struct is as follows: /* Microcontroller FW config */ struct ucode_image_config { uintptr_t src_addr; uint32_t size; }; In DPI-C the code is as follows: /*…

c system-verilog system-verilog-dpi

asked Jul 31 '23 at 18:38

R. de Rojas

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2 answers

In DPI-C, How to map data type to reg or wire

I am writing a CRC16 function in C to use in System Verilog. Requirement as below: Output of CRC16 has 16 bits Input of CRC16 has bigger than 72 bits The difficulty is that I don't know whether DPI-C can support map data type with reg/wire in System…

system-verilog system-verilog-dpi

asked Feb 07 '23 at 07:29

Trong Tran

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1 answer

System verilog simulation performance for uvm_hdl_read vs assign statement

I need to generate around 10,000 connectivity assertions to check that values driven at DUT interface at the beginning of simulation has reached (and is retained) at around 10,000 points inside the DUT throughout the simulation. The 10k destination…

system-verilog uvm system-verilog-dpi

asked Jan 14 '23 at 07:52

thorondor1990

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1 answer

Unpacking system verilog packed struct in DPI-C call

I have a very complicated packed struct, C, with nested packed structs, A and B, in SystemVerilog: typedef struct packed { logic [31:0] ex1; logic [3:0] ex2; } A; typedef struct packed { logic ex3; A [7:0] ex4; } B; typedef struct…

c++ system-verilog system-verilog-dpi

asked Jul 09 '22 at 01:24

Kylie

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1 answer

Get port name in SystemVerilog

I wonder if the modules have any visibility into the hierarchy of the ports? Can the port hierarchy be printed out? For a minimum working example, assume I have this: module top (); logic my_sig; child ichild (.sig(my_sig)); endmodule :…

system-verilog system-verilog-dpi

asked May 19 '22 at 17:00

deejay

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1 answer

how to print from c side with Verilog or SystemVerilog

The question was how to log data from C model into terminal while running test. The answer is using vpi_print in C code instead of regular printf. I have got some strikes for this question and have desided to make it clear. The original version is…

system-verilog system-verilog-dpi

asked Sep 07 '21 at 07:21

Alexandr Bolotnikov

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1 answer

System Verilog to Specman E

What is the equivalent syntax in Specman E for $readmemh(file,array) and similar system tasks and functions in System verilog? I am working in converting the existing System verilog code into Specman E ,I have converted and implemented most of the…

system-verilog specman system-verilog-dpi

asked Jul 30 '19 at 04:31

Sreejin TJ

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1 answer

How to manually compile shared dpi lib?

I try to import some C-function that generates an array in SystemVerilog. Here is code: #include "svdpi.h" #include #include #include void getPacket(int packetSize, svOpenArrayHandle fpSig, svOpenArrayHandle err) { …

c system-verilog system-verilog-dpi

asked Jul 06 '19 at 18:14

Андрей Солодовников

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1 answer

Type erasure in SystemVerilog / DPI

Is it possible to cast SystemVerilog struct to some type-erased pointer, like void *? I need to pass objects of different struct types from SV to C. And I want to have a single DPI function to handle any kind of supported struct. On SystemVerilog…

system-verilog system-verilog-dpi

asked Jun 18 '19 at 21:16

random

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1 answer

Warning: (vsim-8634) Code was not compiled with coverage options

I am trying to run a UVM simulation and I use a C code for predicting the output but I get the warning mentioned above when running the simulation. Will this warning affect the test? Note : I didn't put the importing file for C code in a module. I…

system-verilog uvm system-verilog-dpi

asked Oct 14 '18 at 20:46

Rana Yehya Mohamed

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2 answers

System Verilog DPI - Running parallel threads one in cpp and other in SV

I have a fork-join_none block in forever loop in SV which has two threads. One thread is a call to a task in SV itself. The other thread is a call to a function imported from CPP. Is it possible to run these two threads in parallel? I tried this but…

c++ parallel-processing system-verilog dpi system-verilog-dpi

asked Aug 27 '18 at 04:54

Rahama Tulla

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2 answers

Is it possible to call export function in VPI callback

I have the following scenario : I have a vpi callback that is triggered when an assertion is triggered. In this callback I want to call an export system verilog function I tried to setSvScope before the export but simulator gives me some errors.

system-verilog system-verilog-assertions system-verilog-dpi vpi

asked Jan 10 '18 at 14:18

Viktorinox

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2 answers

Exporting task of an instantiated module

I am trying to export several tasks to a C program via DPI-C. The tasks are defined in the module "my_subm" as: module my_subm; task mytask1(...); ... endtask task mytask2(...); ... endtask endmodule And in my main module…

system-verilog system-verilog-dpi

asked Nov 09 '17 at 10:56

DogTag

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2 answers

Forcing multiple wires in design in SV/UVM

I'm new to System Verilog and UVM, and I've already seen this thread: Regex in SV or UVM I can't find anywhere a proper example on what kind of syntax should I use to force multiple wires in a design, using regular expressions/wildcards. For…

verilog system-verilog verification uvm system-verilog-dpi

asked Oct 04 '17 at 09:38

EEliaz

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1 answer

Error in reading value from SV in C++ function using DPI

I am trying to pass a string from SV to C++ function but the value is not getting passed properly to C++ function Code in SV side: import "DPI" function string mainsha(string str); class scoreboard ; string text_i_cplus; string…

c++ system-verilog system-verilog-dpi

asked Oct 03 '17 at 21:24

Saurabh

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