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Questions tagged [riscv]

For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use. Note: Questions on hardware implementation will be more appropriate for the electronics engineering site: https://electronics.stackexchange.com

Summary

RISC-V (pronounced "risk-five") is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Features

  • A completely open ISA that is freely available to academia and industry.

  • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.

  • An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, and FPGA), but which allows efficient implementation in any of these.

  • An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

  • Support for the revised 2008 IEEE-754 floating-point standard.

  • An ISA supporting extensive user-level ISA extensions and specialized variants.

  • 32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.

  • An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.

  • A fully virtualizable ISA to ease hypervisor development.

  • An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

References

1220 questions
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RISCV function using registers

What is the returning value of this code using RISCV consider c the form is int fun(int n) fun: addi s0, zero, 0 addi s1, zero, 1 add t0, zero, a0 loop: beq s0, t0, exit add s1, s1, s1 addi s0, s0, 1 jal zero, loop exit: add a0, zero, s1…
Yassen Gamal
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load 32 bit immediate value in RISCV memory

I am trying to store a 32 bit immediate value in a riscv memory location.The corresponding code is lui x13,0x12345 addi x13,x13,0x678 // 32 bit value- 12345678 lui x11, 0x1c010 // address location 1c01000 sw x13,x11 The problem I am facing is…
RISCV
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Makefile can I execute a configuration only once?

Im trying to create a Makefile which compiles some files and creates some outputs but first I want it to execute the configuration only one time and the next time I type make it wont re-execute the configuration unless I change the parameters for…
John Liko
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PULP SDK (platform-rtl)

I'm following the tutorial on PULP SDK build process "https://github.com/pulp-platform/pulp-sdk/blob/b38dabd571287b6183f17a2c5538382b9d3fe668/README.md". I'm blocked at the stage of SDK build when I tape the command "$ make all" and I can't…
shp
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How can I Convert M-file to RISC-V Assembly code?

I am new to RISC-V. I want to convert that MATLAB code(M-file) to RISC-V Assembly code, can anyone give some suggestions or inputs on how can I do it. Regards, Yulia
Yulia
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2 answers

How are rs1 & rs2 fields for floating point registers (f0-f31) encoded in RISC-V Instructions?

The Integer register encoding corresponds to their numeric names (0-31, for x0-x31). What is this encoding for f0-f31? I am trying to write a disassembler.
Refpga
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How to put files into riscv linux?

ri 1.We tried to install the rocket chip with risc-v linux on Zedboard, and we had successfully entered riscv linux. However, we couldn't put the files compiled by assembler(using the instruction : riscv64-unknown-linux-gnu-g++) into riscv linux.…
jjlin
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2 answers

errors when installing riscv-tools

I try to install the riscv-tools following the instructions from http://riscv.org/software-tools/. However, I meet problems when I build riscv-isa-sim and the error information is as follows: Error information when build the riscv-isa-sim I am…
xun
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What are the new architecture research in micro-processor design?

While going through research papers I felt that micro-processor architecture is almost saturated. Could any one explain what are the new research happening in micro-processor design.
Aneesh Raveendran
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How can I convert recursive C++ code to RISC-V assembly code and Printing both strings and numbers in RISC-V assembly code for recursive C++ code?

#include using namespace std; //Reference: https://www.geeksforgeeks.org/print-sums-subsets-given-set/ //==============testcase1============== int arr[] = { 5, 4, 3 }; int n = 3; //output: 12 9 8 5 7 4 3…
Thitiwat Thongprasertsang
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Please, can someone explain me what does this assembly code do?

codeA: .data N: .word 10 V: .word 90,50,40,20,30,10,80,70,60,100 .text main: li t2, 0 //t2 <-0 la t3, N //t3 <- @N lw t3, 0(t3) //t3<- N la t4, V //t4 <- V addi a7, x0, 1 //a7 <- i <- 1 p1: beq t2, t3, end lw a0, 0(t4) // a0 <- V[?] ecall addi t2,…
Mims Delama
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Different ISA binary profiling results contradiction

I am doing profiling of my code written in CPP targeting RISC architecture. I have two binaries generated one for x86 and other for RISC-V. I have done profiling using perf and gprof. As per Theory of RISC and CISC architecture,but what I have got…
Yulia
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Header of file compiled by bluespec

I have a file with the .bo extension. After some researches it seems be built with bluespec which is use with risc-V architecture. My objective is to reverse this file. When i do: file myfile.bo myfile.bo: data So, I don't know if it's a good…
Radion
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1 answer

What's the floating point division/square root algorithm of UC Berkeley hardfloat?

Recently, I have been studying the code of berkeley-hardfloat(https://github.com/ucb-bar/berkeley-hardfloat/blob/master/src/main/scala/DivSqrtRecF64_mulAddZ31.scala). I have drawn the timing diagram of DivSqrtRecF64ToRaw_mulAddZ31, but I couldn't…
MK.Bin
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Do you know any simple multicore risc-v?

I'm looking for a simple single-cycle multicore RV32I risc-v implementation, which is written in VHDL or Verilog (VHDL will be the best). Is important that the processor is super simple multicore, without any branch prediction, speculative…
krzmoz
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