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Questions tagged [riscv]

For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use. Note: Questions on hardware implementation will be more appropriate for the electronics engineering site: https://electronics.stackexchange.com

Summary

RISC-V (pronounced "risk-five") is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Features

  • A completely open ISA that is freely available to academia and industry.

  • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.

  • An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, and FPGA), but which allows efficient implementation in any of these.

  • An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

  • Support for the revised 2008 IEEE-754 floating-point standard.

  • An ISA supporting extensive user-level ISA extensions and specialized variants.

  • 32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.

  • An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.

  • A fully virtualizable ISA to ease hypervisor development.

  • An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

References

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JAL: what is the "alternate link register" x5 for?

The RISC-V specification v2.2 (JAL instruction, page 15) says of the "standard calling convention": The standard software calling convention uses x1 as the return address register and x5 as an alternate link register. with the following design…
gasche
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Where are the actual RISC-V instruction codes?

I have downloaded the latest... RISC-V Instruction Set Manual, Volume 1: User-Level ISA ...which is interesting but it never actually gives values for the opcodes/funct3 and other instruction formats. For example, the LOAD/STORE/BRANCH opcodes are…
Phil Wright
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How can I compile C code only for the RV32I base integer instruction and the extension M?

I have started to work with risc-v few days ago, but yesterday I had a problem. The problem is the following: I want to compile code for example for the RV32I base integer instruction set and I want to add too the "M" Standard Extension. When I…
Adriana
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Differences between RISC-V and others ISAs

Can someone explain to me the big differences between ( RISC vs CISC ) vs the RISC-V ISA? I cannot find any relevant difference between CISC and RISC-V on the internet.
Matei
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Why is rv32gc optimising branchless code with branches for RISC-V?

Let's attempt to define a function that returns the maximum of two values x and y. A sufficient condition for these formulas to be valid is that, for signed integers, –2^30 <= x, y <= 2^30 – 1, and for unsigned integers, 0 <= x, y <= 2^31 – 1 (i.e.,…
Hugo Sereno Ferreira
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Buildroot error when building with Ubuntu 21.10

I am trying to compile linux for RISCV Arch using buildroot(busybox). I was using 18.04 and 20.04 previously and had no issues compiling it. Right now, I have upgraded it to 21.10 for building some other stuffs. I have moved my toolchain and I can…
turbo
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GD32VF103 Longan Nano interrupts not working

Introduction: I bought a Longan Nano evaluation board equipped with a GD32VF103 Risc-V MCU. I can run the video player demo, and compile and load working code using VS Code, PlatformIO and the DFU tool. Below a video of the board and the demo…
05032 Mendicant Bias
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How the RISC-V HW can determine the privilege level?

The RISC-V current SW privilege level is not set in any CSR. Nevertheless the spec states that "Attempts to access a CSR without appropriate privilege level ... raise illegal instruction". How can it be implemented then (in the HW)?
Uzi
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Accessing Hardware Performance Counters in RISC-V

I would like to instrument a program to access hardware performance counters. I have compiled a basic Rocketchip (freechips.rocketchip.system-DefaultConfig) and am using riscv-pk to run a binary. I am running a simulation of the core in Verilator,…
Bradley Evans
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How to use an array in RISC-V Assembly

I'm learning RISC-V assembly and i need to use array for an exercise that i'm solving; the problem is that the simulator that i'm using(RARS) gave me an error: Error in /home/username/file_name line 8: Runtime exception at 0x00400010: address out of…
beep
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Why store instructions have their own format

Load and store instructions have the same requirements for encoding: two registers and a 12-bit immediate. However store instructions (sb, sh, sw) have a dedicated format that is called S-type whereas load instructions use the I-type format which is…
Ming
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Setting the mstatus register for RISC-V

I am trying to load mstatus with another register t1. lw t1, mstatus # load mstatys register into t1 xori t1, t1, 0x8 # xor mstatus to set 3rd bit and leave everything else as is lw mstatus, t1 # set mstatus…
Ivan
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Why does JALR encode the LSB of the offset?

We know that jal specifies a 21-bit offset. However, it does not encode a 21-bit offset but a 20-bit one. The reason is that the least significant bit of an address is always zero because the smallest possible RISC-V instruction is 2 bytes, so this…
Lui
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Offset address for JAL and JALR instrctions in RISC-V

In the RISC-V specification, it is written that the immediates in JAL and JALR instructions are converted to jump offsets as : Sign extend the given immediate to XLEN bits. Set the LSB to zero. I have a couple of questions regarding…
ElPsyKongroo
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Speed up large modular multiplication in base 2^8 without multiplier

I am currenty converting the nacl library to risc-v. I already have poly1305 working. I am trying to do this using the risc-v core instruction set, so I don't have a multiplier. The algorithm for Pol1305 is using at the moment ceil(m/16)*17*17 8-bit…
Stefan vd Berg
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