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Questions tagged [riscv]

For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use. Note: Questions on hardware implementation will be more appropriate for the electronics engineering site: https://electronics.stackexchange.com

Summary

RISC-V (pronounced "risk-five") is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Features

  • A completely open ISA that is freely available to academia and industry.

  • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.

  • An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, and FPGA), but which allows efficient implementation in any of these.

  • An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

  • Support for the revised 2008 IEEE-754 floating-point standard.

  • An ISA supporting extensive user-level ISA extensions and specialized variants.

  • 32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.

  • An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.

  • A fully virtualizable ISA to ease hypervisor development.

  • An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

References

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MIPS and RISC-V Differences

I've been trying to learn RISC-V coming from MIPS and initially they don't look to dissimilar, especially the instruction set. Are there any significant differences between the two? Are most of the differences in the backend?
Andrew
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RISC-V Interrupt Handling Flow

I am looking for how a RISC-V processor processes interrupt requests. I looked at the Instruction Set Manuals and information on the internet. The focus is on explaining exactly what the title sets: the instruction set. In my view, how interrupts…
distributed
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Record dynamic instruction trace or histogram in QEMU?

I've written and compiled a RISC-V Linux application. I want to dump all the instructions that get executed at run-time (which cannot be achieved by static analysis). Is it possible to get a dynamic assembly instruction execution historgram from…
noureddine-as
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How can I compile with LLVM/Clang to RISC-V target?

I want to compile a simple program "int main(){return 0;}" to RISC-V processor. LLVM/Clang version is 9.0 and I want to run the compiled program with a RISC-V simulator like this https://github.com/riscv/riscv-tools My problem is that I can't list…
Zoltán
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RISC-V: PC Absolute vs PC Relative

I am new to RISC-V. I am having trouble comprehending when to write PC (Program Counter) relative instructions and when to write PC absolute instructions. For example, an instruction with lui followed by jalr instruction is considered PC-absolute,…
c3r0
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Understanding the auipc+jalr sequence used for function calls

I was trying to read RISC-V assembly generated by gcc and I found that gcc creates sequence of auipc+jalr for some function calls and I don't understand how it works. Here's a simple example. Consider the following C source file: unsigned long…
safsaf32
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Why does RISC-V not have an instruction to calculate carry out?

I need to deal with bignum calculation (addition and subtraction, but I treat subtraction as equivalent to signed addition) on RISC-V and the situation is a bit complicated. What I gather from half an hour of internet research: RISC-V operations do…
piegames
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Mixed destination/source operand order in RISC-V assembly syntax for loads vs. stores

Most instructions in RISC-V assembler order the destination operand before the source one, e.g.: li t0, 22 # destination, source li t1, 1 # destination, source add t2, t0, t1 # destination, source But the store instructions have…
maxschlepzig
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Stack memory operations at the beginning of main function in assembly

I converted a very simple C program to an assembly file (Here, RISC-V ISA), and there were some operations done on the stack pointer that I did not understand. The C program : int main() { int a = 10; return 0; } The associated…
ElPsyKongroo
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Creating A Boot Program in RISC-V

I am trying to create a boot program for RISC-V based boards. I am following this guide, and adapting it for riscv. osdev The problem I'm having is translating this instruction. times 510 -( $ - $$ ) db 0 The best I could think of is to just fill…
christopher clark
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Why does GCC for Risc-V generate nop instructions after call

GCC for Risc-V produces nop instructions after call instructions by default: $ cat test.c void g(); void f() { g(); } $ riscv64-unknown-elf-gcc -S test.c -o - [...] f: addi sp,sp,-16 sd ra,8(sp) sd …
Matthieu Moy
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How to load an immediate number to a register in RV32I Base Instruction Set?

Recently, I am working on RV32I base instruction set, and I did not find any instruction looks like LD r1, imm. Thus, I am wondering how assembly programer load an immediate to a register in RV32I system? Thanks. To do so, programmer could use ADDI…
Betty
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Simulating a CPU design written in Chisel

I've written a single-cycled CPU in Chisel3 which implements most of the RV32I instructions (except CSR, Fence, ECALL/BREAK, LB/SB, which may be included later). The instructions are currently hard coded in the instruction memory, but I will change…
dannebra
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RISC-V ADDI instruction

I am currently working on implementing RV32I Base Instruction Set. I had a question about ADDI instruction. In the manual, how to understand this clause "ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudo-instruction." Does it…
Betty
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How can RISC-V SYSTEM instructions be implemented as trap?

I am currently studying the specifications for RISC-V with specification version 2.2 and Privileged Architecture version 1.10. In Chapter 2 of RISC-V specification, it is mentioned that "[...] though a simple implementation might cover the eight…
Carl Dong
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