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Questions tagged [riscv]

For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use. Note: Questions on hardware implementation will be more appropriate for the electronics engineering site: https://electronics.stackexchange.com

Summary

RISC-V (pronounced "risk-five") is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Features

  • A completely open ISA that is freely available to academia and industry.

  • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.

  • An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, and FPGA), but which allows efficient implementation in any of these.

  • An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

  • Support for the revised 2008 IEEE-754 floating-point standard.

  • An ISA supporting extensive user-level ISA extensions and specialized variants.

  • 32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.

  • An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.

  • A fully virtualizable ISA to ease hypervisor development.

  • An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

References

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RISCV: how the branch intstructions are calculated?

I am trying to understand how modern CPU works. I am focused on RISC-V. there are a few types of branches: BEQ BNE BLT BGE BLTU BGEU I use a venus simulator to test this and also I am trying to simulate it as well and so far so good it works, but…
Kralik_011
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What is meant by FENCE.TSO in the RISC-V ISA?

I don't really understand the difference between a normal FENCE in RISC-V (has been answered here: What is meant by the FENCE instruction in the RISC-V instruction set?) and the FENCE.TSO. The manual says: The optional FENCE.TSO instruction is…
M_eight
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Why is the branch delay slot deprecated or obsolete?

When I reading RISC-V User-Level ISA manual,I noticed that it said that "OpenRISC has condition codes and branch delay slots, which complicate higher performance implementations." so RISC-V don't have branch delay slot RISC-V User-Level ISA manual…
tommycc
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RISCV instructions

I am new to riscv and I am confused between la and lw. I know that la stands for load address and lw stands for load word. If address of VAL is 0x100 and data value of VAL is 0x11 should x3 stores 0x100 and x4 stores 0x11? la x7, VAL sw x3,…
Annonymous119
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How Can I Turn Off RISC-V Compressed Instructions?

When I use the riscv64-unknown-elf-gcc, there is few differences between option -march=rv64g and -march=rv64gc. -march=64g will use RVC codes in standard library functions, for example, the prinft, as much as possible but not in my own functions.…
tuck theo
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Why did RV64 introduce new opcodes for 32-bit operations instead of the 64-bit ones

While going through the RISC-V Specification I've noticed that the 64-bit version differs from the 32-bit one in the fact, that it Widened the registers to 64-bit Changed the instructions to act on the whole 64-bit range. Added new instruction to…
sannaj
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Rocket Chip on Non-Zynq FPGAs

I want to port the rocket chip to a non-Zynq FPGA (an altera Stratix V), a board which doesn't contain an ARM core used to run the riscv-fesvr. How can I go about starting the port? Also, has anyone attempted to run the rocket chip on such a board?…
user2888398
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Why is it recommended to only use registers a0 and a1 to pass return values in RISC-V?

The RISC-V Calling Convention states that registers a0 and a1 can be used for return values, rather than all eight registers a0~a7. When there are more than two values needed "returning", we can use the stack otherwise. Why? Are there any advantages…
adong660
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Converting Python program to C/C++, and then to RISC-V executable

I have been trying to run a Python program on a system with RISC-V architecture. The program involves runs a simple artificial neural network model, and involves the use of numpy. However, the operating system running on the RISC-V archtecture…
Bharath Kinnal
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RISC-V return from exception handler with compressed instructions

I see the standard way of exiting RISC-V exception handler is update mepc to mepc+4 before mret. But won't this cause problem if the next instruction is only 2-bytes long in compressed instruction mode? In compressed instruction mode there are mixed…
ratt
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Any assumption in the RISC-V ISA preventing the stack from growing up rather than down?

I was wondering whether anything in the ISA would make a stack growing up (a push increases sp, a pop decreases it) less performant or otherwise inadvisable? I am aware that this is not how present day tooling works, including Linux and GCC ports,…
Schwanritter
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Convert between big-endian and little-endian on RISC-V

What is the simplest way to work with big-endian values in RISC-V at the assembly language level? That is, how to load a big-endian value from memory into a register, work with the register value in native-endian (little-endian), then store it back…
Lassi
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Adding new instruction to RISCV-32ima: "bad RISCV-opcode"

I'm seeking for help concerning the extensions I'm trying to add to riscv. GLOBAL SETTING My working baseline is a clone of the riscv-tools repo, containing the usual tools, among which are: riscv-fesvr riscv-gnu-toolchain riscv-isa-sim…
Lionel Morel
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Why the immediate offset in the riscv's JAL instruction has bit order changed?

The bit field is shown below I don't see the point the of doing this re-ordering of bit-field. Is there a special kind of manipulation when RISC-V processor is executing this instruction?
jackripper
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RISC-V: Why set least significant bit to zero in JALR

Why do we need to set the least significant bit to zero in JALR in RISC-V Instruction set as described in the RISC-V Instruction manual? Is it for alignment propose?
Ammar Kurd
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