How the RISC-V HW can determine the privilege level?

Question

The RISC-V current SW privilege level is not set in any CSR. Nevertheless the spec states that "Attempts to access a CSR without appropriate privilege level ... raise illegal instruction". How can it be implemented then (in the HW)?

The hardware can (and certainly does) have state that is not exposed to software via registers. — Erik Eidt, Feb 18 '20 at 17:37

score 3 · Answer 1 · answered Feb 20 '20 at 08:55

Well, on interrupts - "xPP holds the previous privilege mode (x=M,S or U). The xPP fields can only hold privilege modes up to x, so MPP is two bits wide, SPP is one bit wide, and UPP is implicitly zero."

Actually, what I have found now is that the xRET instruction enables the processor to store (internally) the current mode - "The MRET, SRET, or URET instructions are used to return from traps in M-mode, S-mode, or U-mode respectively. When executing an xRET instruction, supposing xPP holds the value y, x IE is set to x PIE; the privilege mode is changed to y; x PIE is set to 1; and xPP is set to U (or M if user-mode is not supported)."

score 2 · Answer 2 · answered Mar 08 '20 at 10:58

I found this answer from sifive forums quite helpful when I was looking for the same question.

RISC-V deliberately doesn’t make it easy for code to discover what mode it is running it because this is a virtualisation hole. As a general principle, code should be designed for and implicitly know what mode it will run in. Applications code should assume it is in U mode. The operating system should assume it is in S mode (it might in fact be virtualised and running in U mode, with things U mode can’t do trapped and emulated by the hypervisor).

https://forums.sifive.com/t/how-to-determine-the-current-execution-privilege-mode/2823

I searched and surprised that the current priv mode is not stored as architectural. So, as you said it cannot be detected by software easily. — Ömer GÜZEL, Jun 19 '23 at 11:32

score 1 · Answer 3 · answered Feb 19 '20 at 09:46

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The privilege level is reflected in the MPP bits of the mstatus register.

answered Feb 19 '20 at 09:46

Martin Norbäck Olivers

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score 1 · Answer 4 · answered Mar 01 '20 at 17:56

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We have mstatus.mPP. that holdS the previous privilege mode. Current privilege mode is not visible to software.

on interrupt the mstatus.mPP is saved to mcause.mPP.. on mrwt, its just written back to mstatus.mPP.

answered Mar 01 '20 at 17:56

Rupinderjit

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How the RISC-V HW can determine the privilege level?

4 Answers4