How does the CPU know the PCI adress-space

Question

I understand that PCI and PCIe devices can be configured by the CPU (via code in the BIOS or OS) to respond to certain physical memory addresses by writing to specific areas of the device's configuration space.
In fact the Linux kernel has quite the complicated algorithm for doing this taking into account a lot of requirements of the device (memory alignment, DMA capabilities etc).

Seeing that software seems to be in control of if, when and where this memory is mapped, my question is: How can a piece of software control mapping of physical memory?

After this configuration, the PCI device will know to respond to the given address range, but how does the CPU know that it should go on the PCI bus for those specific addresses that were just dynamically decided?

could you add a link to that algorithm from the linux kernel source (web view)? — n611x007, Aug 01 '14 at 19:05

score 6 · Accepted Answer · answered Oct 27 '13 at 10:17

6

The northbridge is programmed with the address range(s) that are to be routed to the memory controller(s). All other addresses go to the external bus.

answered Oct 27 '13 at 10:17

CL.

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It is not contiguous though is it? Does configuration SW have to fill BAR for each phys. memory range? – Pyjong May 03 '16 at 15:06
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@Pyjong All those accesses go to the bus; the devices themselves decode the addresses. – CL. May 03 '16 at 16:16
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well yes, devices respond to addresses set in their BARs right. – Pyjong May 03 '16 at 17:05
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Yeh, according to Intels manual to (G)MCH there are BARs for all ranges. – Pyjong May 04 '16 at 09:29

score 3 · Answer 2 · answered Aug 20 '19 at 09:54

It is based on address mapping info that CPU had. normally you have 2^64 -1 address lines with CPU if it is 64 bit processor. Now memory is now around 16 GB which is 2^34 is around 16 GB. So all the devices which CPU has (even legacy PCI and PCIe devices) and their config space can be mapped to address line above this RAM physical address space. Any IO to this space can be forwarded to respective device. In our case CPU finds out that the config space which it wants to access to is a PCI or PCIe device then it forwards the instruction to host bridge of CPU (00:00:00 Do lspci in a box you will see the host bridge with this BDF)

Once it finds out the target device is within host bridge the instruction (Can be IO or Memory) will be converted to appropriate TLP request.

How does the CPU know the PCI adress-space

2 Answers2