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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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How does the Memory and IO addresses treated differently in the endpoint device?

Let assume we have two PCIe endpoint devices A and B. A implements MMIO addresses and B implements IO address. How does these endpoints handles these addresses internally ? How it is decided that the endpoint should use MMIO or IO address or both ? …
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Low data rate between two Linux machines connected over PCIe

I am trying to communicate between two Linux based devices (i.e. PowerPC (Big-Endian 32-bit) & ARM (Little-Endian 32-bit)) connected over PCIe. One of the device acts as Root Complex and the other as Endpoint. The devices successfully negotiate to…
Arshan
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Linux PCIe DMA driver

I'm currently writing a driver for a PCIe device that should send data to a Linux system using DMA. As far as I can understand my PCIe device needs a DMA controller (DMA master) and my Linux system too (DMA slave). Currently the PCIe device has no…
fonZ
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Packet generation in PCI PCIe devices

I have few questions on the PCI/PCIe Packet generation and the CRC generation and calculation. I have tried many searches but could not get the satisfactory answer. Please help me to understand the below points. 1.How does Packets(TLP, DLLP and…
dis
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Strange behavior of PCIe throughput when used in OpenCL

Tested the throughput of PCIe with OpenCL and I am getting strange results. I am using PCIe 3, x16. DATA_SIZE = 2097152 (int) Data size bytes = 8.388608 MB The code is following: struct timeval tv1, tv2; gettimeofday(&tv1,…
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BIOS Stuck after PCIe Enumeration

We are developing a custom PCIe card on FPGA. After programming the FPGA, we can read the PCIe configuration and it seems correct. When we connect this PCIe card on a Jetson TX2, it works fine. But, when we connect this on an x86_64 PC, (ASUS PRIME…
Vinu Chandran
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SMBus on PCIe Slot

I have some PCIe cards, which have some PMICs on SMBus. If I connect more than one (identical) PCIe cards on different slots(on an x86), would I be able too access all PMICs (with same address)? Does all the PCIe slots share the same SMBus lines,…
Vinu Chandran
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Is there a way for two custom PCIe cards to talk directly to each on when plugged into a server (no switch)?

We saw this answer: Direct communication between two PCI devices Which goes a long way towards answering the question. But we wanted to poke a bit at it, to see if there's any wiggle room. So, we are making custom PCIe cards, with custom drivers.…
seanhalle
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Memory regions not displayed in 'lspci -vv' while using 'AXI bridge for PCI express Gen3.0 subsystem'

We are developing a system with a custom processor, Microblaze and some peripherals in VC709 FPGA using Xilinx Vivado. We are using two 'PCIe : BARs' in 'AXI Bridge for PCI express'. Initially the command 'lspci -vv' used to show memory regions in…
vineeshvs
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Different order between nvidia-smi and nvidia x server settings

When I run the command nvidia-smi, I get the following two GPUs ordered by their Bus-Ids: For GPU 0, 00000000:0A:00.0 For GPU 1, 00000000:41:00.0 However, when I run NVIDIA X server Settings, I can get the following GPUs ordered by their…
hjung
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Disable PCIe device asserting unknown interrupt

I'm currently working on a PCIe-based Intel network card driver for my OS development project. While the driver seems to be working well, as soon as I enable INTA (IRQ 16, using the I/O APIC) I keep getting a flood of interrupts which completely…
janw
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How does pcie errors are reported to root complex?

Lets say a pci express device implements an AER capability for robust error reporting. So whenever such error is intercepted by the device, it populates its AER register accordingly. How this error will be reported to root complex? I read in spec…
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DMA on FPGA Cannot Access Kernel Memory Allocated with GFP_KERNEL Flag

I would first like to give a brief description of the scenario that I am working on. What I am trying to accomplish is to load image data from my user space application and transfer it over PCIe to a custom acceleration engine located inside a FPGA…
Δημήτριος Μπακογιάννης
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Registering interrupt with irq from pci_irq_vector(9) function results in "No irq handler for this function"?

I am writing a device driver that services the interrupts from the device. The device has only one MSI interrupt vector, so I poll the irq with pci_irq_vector(dev, 0), receive the irq, and register the interrupt. This is shown in the following code…
Cain Rose
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How does BIOS determine the PCI port type during enumeration process?

As in PCI Express a capability register called “pci express capability register” specifies the device/port type field which tells whether its root port, upstream switch port, switch downstream port, end point etc. What mechanism does BIOS use to…
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