Modelsim VHDL Array Initialization gives warning (vcom-1320)

Question

I'm using Modelsim's VHDL-Compiler (vcom) for code linting with SublimeText (VHDL 2008). While initializing an array of standard_logic_vector I get the following warning:

vcom: warning Warning - (vcom-1320) Type of expression "(OTHERS => '0')" is ambiguous; using element type STD_LOGIC_VECTOR, not aggregate type t_a_reg.

A minimal code example is as follows:

library ieee;
use ieee.std_logic_1164.all;

entity module is
  port
  (
    clk : in std_logic;
    rst : in std_logic;
    ...
  );
end entity;

architecture rtl of module is

  type t_a_reg is array (integer range <>) of std_logic_vector(15 downto 0);
  signal s_event_reg : t_a_reg(1 downto 0) := (others => (others => '0'));   -- this gives the warning

  ...

begin
  ...

end architecture;

I checked in Modelsim by typing verror 1320 in the tcl console, which gives the following explanation:

vcom Message # 1320: The expression of each element association of an array aggregate can be of the element type or the type of the aggregate itself. When an array aggregate is of an array type whose element subtype is composite, it is possible for certain kinds of its element association expressions to be interpreted as being potentially either of these two types. This will normally happen only if the ambiguous expression is itself an aggregate (because the type of an aggregate must be determined solely from the context in which the aggregate appears, excluding the aggregate itself but using the fact that the type of the aggregate shall be a composite type) or a function call that identifies two overloaded functions. This ambiguity is resolved in favor of the element type to support backwards compatibility with prior versions of VHDL, in which the element type was the only type considered. [DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates]

I found two ways to initialize the array without getting the warning, but both have flaws.

The first is problematic, if the size of the std_logic_vector changes, since I have to modify the initialization:

  type t_a_reg is array (integer range <>) of std_logic_vector(15 downto 0);
  signal s_event_reg : t_a_reg(1 downto 0) := (others => x"0000");            -- no warning

The second method is quite verbose and I don't like that very much:

  subtype t_vec is std_logic_vector(15 downto 0);
  constant c_vec_init : t_vec := (others => '0');
  type t_a_reg is array (integer range <>) of std_logic_vector(15 downto 0);
  signal s_event_reg : t_a_reg(1 downto 0) := (others => c_vec_init);        -- no warning

The question is: Is there a correct VHDL-2008 way of initializing the array, so I don't get the warning? The question is more of a philosophical one, since the code works. I'd just like to know, if I'm missing something.

Thanks in advance!

Peter

Edit: I forgot to mention, I also tried a qualified expression:

  type t_a_reg is array (integer range <>) of std_logic_vector(15 downto 0);
  signal s_event_reg : t_a_reg(1 downto 0) := (others => std_logic_vector'(others => '0'));

This however produces a real error:

vcom: error - Error - (vcom-1076) OTHERS choice cannot be used in unconstrained array aggregate.

It's always a good idea to track down and eliminate warnings. Even if none of the current warnings are important, if you're used to just ignoring them you might miss an important one in the future. — Matthew Taylor, Jul 14 '20 at 12:35
Can you submit this example to the 1076 working group at http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome — Jim Lewis, Jul 14 '20 at 15:13
Have you tried: ` signal s_event_reg : t_a_reg(1 downto 0) := (1 downto 0 => (others => '0'));` — Jim Lewis, Jul 14 '20 at 15:14
@JimLewis thanks for the input. I just tried and the warning persists. `signal s_event_reg : t_a_reg(1 downto 0) := (others => (15 downto 0 => '0'));` as well as `signal s_event_reg : t_a_reg(1 downto 0) := (1 downto 0 => (15 downto 0 => '0'));` don't make a change either. Also: How do I submit this example to the 1076 working group? Send it via e-mail to Pete Ladow or do I have to create a new topic? — Peter, Jul 14 '20 at 15:24
@Peter IEEE WG has a new place for submitting issues. You need a gitlab account (free signup). https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues — Jim Lewis, Jun 01 '21 at 14:58

score 1 · Answer 1 · answered Jul 14 '20 at 12:37

1

How about using a type qualification:

signal s_event_reg : t_a_reg(1 downto 0) := (others => std_logic_vector'(others => '0'));
--                                                     ^^^^^^^^^^^^^^^^^

answered Jul 14 '20 at 12:37

Matthew Taylor

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Unfortunately not. I forgot to mention, I tried this one (I'll add it to the question). Doing so produces a real error (vcom: error - Error - (vcom-1076) OTHERS choice cannot be used in unconstrained array aggregate.) – Peter Jul 14 '20 at 12:41

Modelsim VHDL Array Initialization gives warning (vcom-1320)

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