Load-link/Store-conditional (LL/SC) is a pair of instructions used for synchronization.
Questions tagged [load-link-store-conditional]
15 questions
11
votes
2 answers
compare-and-swap atomic operation vs Load-link/store-conditional operation
Under an x86 processor I am not sure of the difference between compare-and-swap atomic operation and Load-link/store-conditional operation. Is the latter safer than the former? Is it the case that the first is better than the second?
Guillaume Paris
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9
votes
2 answers
When is CLREX actually needed on ARM Cortex M7?
I found a couple of places online which state that CLREX "must" be called whenever an interrupt routine is entered, which I don't understand. The docs for CLREX state (added the numbering for easier reference):
(1) Clears the local record of the…
Lou
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6
votes
2 answers
How is a spin lock woken up in Linux/ARM64?
In the Linux kernel, arch_spin_lock() is implemented as follows:
static inline void arch_spin_lock(arch_spinlock_t *lock)
{
unsigned int tmp;
arch_spinlock_t lockval, newval;
asm volatile(
/* Atomically increment the next ticket.…
pranith
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4
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1 answer
What' s the advantage of LL/SC when compared with CAS (compare-and-swap)?
What' s the advantage of LL/SC comparing with CAS(compare and swap) in computer architecture? I think LL/SC can case livelock in many-core system, and case ABA problem, but CAS does not. I can not find out any advantage of LL/SC comparing with CAS.…
winter
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4
votes
2 answers
ARM LL/SC exclusive access by register width or cache line width?
I'm working on the next release of my lock-free data structure library, using LL/SC on ARM.
For my use-case of LL/SC, I need to use it with a single STR between the LDREX and STREX. (Rather than using it to emulate CAS.)
Now, I've written the code…
user82238
3
votes
1 answer
Lock-free C++11 example using Load-link/store-conditional to prevent ABA?
When writing lock-free code using the Compare-and-Swap (CAS) technique there is a problem called the ABA problem:
http://en.wikipedia.org/wiki/ABA_problem
whereby comparing just on the value "A" is problematic because a write could still have…
user997112
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2
votes
0 answers
In risc-v architecture, how does store conditional instruction realize that the memory is modified?
The following code snippet is from Computer Organization and Design, RISC-V edition, 2nd edition.
Suppose that the memory location that is addressed by x20 register is modified after execution of lr.w instruction and before execution of sc.w. My…
user153245
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2
votes
1 answer
How is this a guarantee a value has been atomically updated in ARM?
ARM provides LDREX/STREX to atomically load/store values, but I feel like I'm missing something in how this is still an atomic operation. The following below is generally how an increment by one would be done. However, what's preventing something…
Maxthecat
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1
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1 answer
__sync_add_and_fetch triggers an sError interrupt on raspberry pi 4b
When I use gcc's __sync_add_and_fetch to atomically increment an integer on my raspberry pi4b, the following code is generated:
172e4: c85f7e60 ldxr x0, [x19]
172e8: 91000400 add x0, x0, #0x1
172ec: c801fe60 …
freewill
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1
vote
1 answer
Does lock can avoid lr/sc 'spuriously fail'
I learn 'Computer Organization and Design' RISC-V version by David A. Patterson, and on page 254 Elaboration have below code
below is book contents and related code:
While the code above implemented an atomic exchange, the
following code would more…
zg c
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1
vote
1 answer
Implementing global monitor for exclusive access
Am implementing a global monitor for exclusive access (for ARM cores).
Query- if a particular exclusive transaction is successful, should I signal a clear on the global monitor?
In the case above is required, a concern is this would cause other…
user10367180
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1
vote
0 answers
What's 'reservation' in RISC-V's 'lr' instruction?
From 8.2 Load-Reserved/Store-Conditional Instructions chapter in RISC-V's unprivileged ISA Manual,
LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that subsumes the…
Wanghz
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1
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1 answer
atomic linked-list LIFO in AArch64 assembly, using load or store between ldxr / stxr
I had implemented a LIFO for shared memory context using assembly for ARMv8 64bit.
The LIFO inserts a node in beginning and each node structure's first attribute must be next pointer.
Is this correct assembly for implementing atomic insert and…
souradeep
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1
vote
0 answers
ARM Cortex-M4/7: Do regular memory accesses between LDREX/STREX invalidate the exclusive monitor
I am trying to rewrite a code section that currently works with disabling/enabling interrupts with LDREX/STREX on a STM32F7(single core, microcontroller).
May sound like a straightforward question, but after a couple of days researching, did not…
Dan
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1
vote
2 answers
How do ldrex / strex make atomic_add in ARM an atomic operation?
As per http://lxr.free-electrons.com/source/arch/arm/include/asm/atomic.h#L31
static inline void atomic_add(int i, atomic_t *v)
41 {
42 unsigned long tmp;
43 int result;
44
45 prefetchw(&v->counter);
46 …
user435739