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From 8.2 Load-Reserved/Store-Conditional Instructions chapter in RISC-V's unprivileged ISA Manual,

LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written.

What's the reservation in the description? How is it implemented in hardware? How does a Hart know if the reservation has been invalidated by another Hart?

Peter Cordes
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Wanghz
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    Presumably it notices if the cache line leaves exclusively-owned state between the LL and the SC. As far as software is concerned, it's an LL/SC like on MIPS, ARM, PowerPC, etc. https://en.wikipedia.org/wiki/Load-link/store-conditional even mentions "load reserved" as a synonym. SO actually has a tag for that, although IDK if any specifically ask how the hardware works, e.g. ARM's "monitor" region. https://stackoverflow.com/questions/tagged/load-link-store-conditional – Peter Cordes Dec 06 '21 at 07:40
  • @PeterCordes So `reservation` can be viewed as a flag maintained by hardware. Maybe CPU can monitor changes on the same address accessed by `lr` through cache line or some other hardware components if there's no cache. That's fine for me as I'm a software guy. Thank you. – Wanghz Dec 06 '21 at 10:28
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    Yes, the reservation is like a flag: look at the operation of the `SC` instruction: it is conditional AND it tells you if it worked or not, with an boolean output of the result going to `rd`. If it didn't work, you can retry with a short spin loop. – Erik Eidt Dec 06 '21 at 15:43

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