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What' s the advantage of LL/SC comparing with CAS(compare and swap) in computer architecture? I think LL/SC can case livelock in many-core system, and case ABA problem, but CAS does not. I can not find out any advantage of LL/SC comparing with CAS. Anyone can tell me?

Flow
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winter
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  • There is a basic comparison [here](https://en.wikipedia.org/wiki/Load-link/store-conditional#Comparison_of_LL.2FSC_and_compare-and-swap). – Jason Aug 19 '15 at 14:26
  • Thanks for your answer. The comparison is too simple. I want to know the detailed performance comparison. – winter Aug 20 '15 at 15:46

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Since nobody has answered, LL/SC does not suffer from the ABA problem since the conditional store will fail if the address referenced by the LL is modified. Furthermore, it can't livelock since one or more LL/SC pairs failing implies another succeeded. A CAS could also potentially be more expensive, since it may require the invalidate queue be flushed.

Jason
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  • Thanks for your answer. Now I know that the LL/SC exactly does not suffer from the ABA problem because context switch will case SC fail. But, when too many other LL(s) happen from other cores between LL and SC, there will case livelock, for the season that LL from other core will case SC fail. – winter Aug 20 '15 at 15:53
  • @winter I'm not sure I completely understand what your describing. Can you update your question with what you don't understand or you want to know? – Jason Aug 20 '15 at 18:04
  • Implementations using LL/SC can yield a live-lock situation under certain circumstances. I think the basic case is when two hardware threads invalidate the LL/SC operation of each other. That is why there are restrictions in what you can do between LC and SC. See also https://yarchive.net/comp/linux/cmpxchg_ll_sc_portability.html and the RISC-V manual discussing LR/SC and "constrained LR/SC sequences" in particular. – Flow Jan 08 '20 at 15:37
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    @Flow: It's not what one thread does between *its own* LL and SC that's the problem, it's that even a MESI share request (for read-only access to a cache line) can cause the SC to fail. (Because the core that previously owned it has to transition out of Modified or Exclusive state, and SC depends on the line having stayed in one of those states since the LL, guaranteeing that no other core could see the inside of the atomic operation). I would guess that high-performance multicore CPUs favour delaying MESI response to give LL/SC more chance to complete and avoid livelock, or something. – Peter Cordes Jan 08 '20 at 17:26