Timing diagram of convst. signal of ADC (ads8556)

Question

I want to work on ADC (ads8556). In Figure 3 In the Parallel Read Access Timing Diagram, when the conversion time (tconv) finishes, and during the acquisition time (tACQ), there are multiple transitions in the level state of convst signal changes between 0 and 1. This transition between 0 and 1 is not clear for me. Can anyone tell me if it is optional or not?

The timing diagram is shown in the figure.

I am working of ads8556 with FPGA de2i-150. But I don't understand the timing diagram.

I think you ask for the transition from 1 to 0 of CONVST_A/B/C (and not for the transition from 0 to 1). This transition is shown with several edges, as the exact timing is not specified. So you are free to change the signal from 1 to 0 at any time after tconv and must only guarantee t1 which is the minimal "CONVST_x low time". — Matthias Schweikart, Jun 23 '23 at 09:29
This question is more appropriate for https://electronics.stackexchange.com. I flagged it for migration to that site. — toolic, Jun 23 '23 at 10:51

score 0 · Accepted Answer · answered Jun 23 '23 at 10:07

This kind of "multi-edge" in a timing diagram means that the single(!) edge occurs

at the earliest when the first edge is drawn;
at the latest when the last edge is drawn.

The exact moment in this range is irrelevant. You can put CONVST_x to low any moment after BUSY became low. (Actually, you can set it low before, but: "A falling edge during an ongoing conversion puts the related ADC pair into partial power-down mode, see the Reset and Power-Down Modes section for more details.")

The interval t₁ is required to be ≥ 20 ns according to the data sheet, but it can be longer. The ADC just needs this interval to detect the rising edge of the next conversion start reliably.

Timing diagram of convst. signal of ADC (ads8556)

1 Answers1