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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Why does int addition though pointers take one less x86 instruction than int multiplication through pointers?

I have the following C/C++ code (compiler explorer link): void update_mul(int *x, int *amount) { *x *= *amount; } void update_add(int *x, int *amount) { *x += *amount; } Under both clang and gcc compiling as C or as C++ with at least…
nullUser
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Why different ranges of permitted shift values for ARM LSL vs LSR?

Why is permitted shift value of LSL [0, 31] and permitted shift value of LSR is [1, 32]? How is shifting 0 bits in LSL useful for any application? Why is 0 shift not allowed in LSR? Why doesn't LSL allow 32-bit shifts?
Vighnesh Nayak
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68k register addresses

This question is begging for a bunch of "why are you doing this?" responses. I haven't been able to find this information in the 68k Programmer's Reference Manual, but that may be because I'm not sure of what verbiage to search for. Here is the…
mwcz
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Disabling all AVX512 extensions

I need to disable all AVX512 extensions in gcc-compiled code. The reason is that Valgrind chokes on AVX512 instructions. Is there a way to do it with a single flag? I know how to disable each extension individually (-mno-avx512f, -mno-avx512pf etc)…
n. m. could be an AI
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When to use CMP & TEQ instructions in ARM Assembly?

why two separate instructions instead of one instruction? Practically in what kind of situations we need to use CMP and TEQ instructions. I know how both the instruction works.
Rakesh N Rakesh
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What optimizations are shipped in Intel Distribution for Python?

Intel strongly recommends using their distribution for Python, instead of manually building Python modules for yourself. An obvious advantage is that there are many optimized modules available from their distribution, a non-trivial task if you want…
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How does LUI/ORI on MIPS work to create a 32-bit constant value?

I have this risc v code : lui S0, 0x1234 ori S1, S0, 0x5678 add S2, S1, S1 and the question asks me, "What does the register S2 hold?" The question explains that lui and I quote: "Load the lower half word of the immediate imm into the upper…
Razi Awad
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x86 microarchitecture/SIMD market share

Where can I find data about "market share" of x86 microarchitectures? What percentage of users of x86-family CPUs have a CPU that supports SSE4.2, AVX, AVX2, etc.? I'm distributing precompiled binaries for my program, and I would like to know what…
Kornel
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Why are there two ways to multiply arbitrary signed numbers in MIPS?

If you need to multiply two arbitrary signed numbers in MIPS, is there a reason to prefer: mul $t0 $s0 $s1 Or this: mult $s0 $s1 mflo $t0 ? I'm finding inconsistent answers online with regard to what each one means. At first glance I would expect…
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add3 instruction for a+b+c with one single rounding

Background It is well known that the exact product of two floating point numbers is not always a floating point number, but the error exact(a*b) - float(a*b) is. Some codes for exact multiplication exploit this by returning the two numbers res = a *…
Nico Schlömer
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How to go From Assembler instruction to C code

I have an assignment where, among other things, I need to look in an .asm file to find a certain instruction and "reverse engineer" (find out) what part of the C code causes it to be executed on an assembler level. (Example below the text) What…
vandelfi
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Why doesn't MIPS have a Store Immediate instruction just like Load Immediate instruction?

MIPS has a Load Immediate (LI) pseudo instruction to load a 32-bit immediate value into a register. But it does not have Store Immediate (SI) instruction to store a 32-bit immediate value to Memory. Can someone explain me why?
sandywho
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What is the difference between Instruction Set and Instruction Set Architecture (ISA)?

I am not able to understand the difference between Instruction set and Instruction set architecture. I know what is an instruction set. Instruction set just defines the possible instructions we can give to the processor and how the instruction are…
d4rkl0rd
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Understanding FMA instructions performance

i'm tring to understand how can i max out the number of operations i can get on my CPU. I'm doing a simple matrix multiplication program, and i have a Skylake processor. I was looking at the wikipedia page for the flops information on this…
Peter L.
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How do I decode a machine instruction to assembly in LEGv8?

I am having trouble figuring out how a LEGv8 machine instruction is decoded. Assume the following binary: 1000 1011 0000 1111 0000 0000 0001 0011 I have the following chart that is supposed to help me decode: The first 11 bits 10001011000…
Jason Fel
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