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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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What exactly does the 3-operand imul instruction do in ia-32 assembly?

I'm reading the instruction imul 0xffffffd4(%ebp, %ebx, 4), %eax and I'm baffled by what it's doing exactly. I understand that imul multiplies, but I can't figure out the syntax.
Rowhawn
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how to write XOR in assembly(ARM)

I want to get xor value of two register.But compile return error how to write XOR in assembly(ARM) XOR r1,r1,r0; compiler gives like error, Error: bad instruction `xor r1,r1,r0'
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What do the abbriviations (Rn, Rd, ...) in the instruction set of ARM mean?

recently i checked the Instruction Set for an ARM Cortex-M3 processor. For example: ADD , , What do those abbriviations mean exactly? I guess they mean different kinds of addresses, like directely addressed, relatively addressed or…
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Why isn't movl from memory to memory allowed?

I was wondering if this is allowed in assembly, movl (%edx) (%eax) I would have guessed that it access the memory in the first operand and puts in the memory of the second operand, something like *a = *b but I haven't seen any example dealing…
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How can I tell if jump is absolute or relative?

I'm studying for a test in assembly and in the subject of "Position-Independent-Code" I find the difference between a relative jump and an absolute jump confusing. How can I tell what kind of jump it is? I understand what a relative jump is (the…
lolu
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List of Cortex-M4 Opcodes

I've been looking for a list of the opcodes used in ARM Cortex M3/M4/M4F, without luck. There are plenty of [online] references to the 32-bit format of ARM instructions. References to Thumb-2 instructions are scarce, but available. The version used…
Alan Campbell
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how verify that operating system support avx2 instructions

I have configuration: Intel(R) Core(TM) i7-4702MQ CPU (with Haswell architecture), Windows 8, Intel C++ Compiller XE 13.0. I want run my program with avx2 optimization and put compilation flags: /QaxCORE-AVX2, /QxCORE-AVX2 But when I run the…
Konstantin Isupov
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New instruction sets in CPU

Every new generation of CPU introduces some sets of new instructions, i.e. MMX, 3DNOW, SSE and so on. I've got few general questions about them: If some program uses for example SSE instruction can it be run on CPU that doesn't support SSE? If yes,…
Tomek Tarczynski
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How does the CPU/assembler know the size of the next instruction?

For the sake of example, imagine I was building a virtual machine. I have a byte array and a while loop, how do I know how many bytes to read from the byte array for the next instruction to interpret an Intel-8086-like instruction? EDIT:…
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Do I need to make multiple executables for targeting different instruction sets?

Consider I have a program to do AES operations. Some advanced CPUs have AES-NI instruction set, and other CPUs don't have. Must I compile my program into two executables: A_with_aes_ni.exe and B_without_aes_ni.exe ?
xmllmx
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What is -(-128) for signed single byte char in C?

My little program: #include int main() { signed char c = -128; c = -c; printf("%d", c); return 0; } print: -128 Is minus (-) operator portable across CPU?
gavenkoa
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cpuid instruction on i5-2500k: MMX, SSE, SSE2 bits are not set

Is this expected? I expected my Sandy Bridge CPU to report that it can handle MMX, SSE, and SSE2 instructions. Are these bits not set because these "old" instruction sets have been "superceded" by some of the newer ones? I used this code here to…
Steven Lu
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Reference for x86 instructions by functionality

I am looking for a reference on the "evolution" of x86 instruction set. Mainly, which newer commands make older commands redundant and unusable and a breakdown of the instruction according to their functionality and not to the time/processor they…
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Is there a list of unused binary opcodes for X86_64 (amd64)

I am trying to add custom instructions in X86_64 (amd64) ISA. I will create a binary using these instructions and then I'll run it in gem5 simulator. To find the list of unused opcodes, I am referring to http://ref.x86asm.net/coder64.html. However,…
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Organizing multiple implementations (for SIMD)

This is admittedly an open-ended/subjective question but I am looking for different ideas on how to "organize" multiple alternative implementations of the same functions. I have a set of several functions that each have platform-specific…
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