Stack Overflow
Stack Overflow

Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

736 questions
7
votes
3 answers

How is fma() implemented

According to the documentation, there is a fma() function in math.h. That is very nice, and I know how FMA works and what to use it for. However, I am not so certain how this is implemented in practice? I'm mostly interested in the x86 and x86_64…
the swine
  • 10,713
  • 7
  • 58
  • 100
7
votes
2 answers

How is a relative JMP (x86) implemented in an Assembler?

While building my assembler for the x86 platform I encountered some problems with encoding the JMP instruction: OPCODE INSTRUCTION SIZE EB cb JMP rel8 2 E9 cw JMP rel16 4 (because of 0x66 16-bit prefix) E9 cd JMP rel32 …
Pindatjuh
  • 10,550
  • 1
  • 41
  • 68
7
votes
5 answers

How many byes is each instruction compiled to in x86 assembly?

0x004012d0 : push %ebp 0x004012d1 : mov %esp,%ebp 0x004012d3 : sub $0x28,%esp If the address is not available, can we calculate it ourselves? I mean we only have this: push %ebp mov %esp,%ebp sub …
Mask
  • 33,129
  • 48
  • 101
  • 125
7
votes
2 answers

assembly "mov" instruction

I'm learning assembly by comparing a c program to its assembly equivalent. Here is the code. .file "ex3.c" .section .rodata .LC0: .string "I am %d years old.\n" .LC1: .string "I am %d inches tall.\n" .text .globl main .type…
user2263800
  • 193
  • 1
  • 3
  • 8
7
votes
3 answers

xorl %eax - Instruction set architecture in IA-32

I am experiencing some difficulties interpreting this exercise; What does exactly xorl does in this assembly snippet? C Code: int i = 0; if (i>=55) i++; else i--; Assembly xorl ____ , %ebx cmpl ____ , %ebx Jel .L2 ____ %ebx .L2: ____…
Hélder Moreira
  • 181
  • 1
  • 1
  • 9
7
votes
3 answers

Which arithmetic operations are the same on unsigned and two's complement signed numbers?

I'm designing a simple toy instruction set and accompanying emulator, and I'm trying to figure out what instructions to support. In the way of arithmetic, I currently have unsigned add, subtract, multiply, and divide. However, I can't seem to find a…
joshlf
  • 21,822
  • 11
  • 69
  • 96
7
votes
2 answers

Differences between RISC-V and others ISAs

Can someone explain to me the big differences between ( RISC vs CISC ) vs the RISC-V ISA? I cannot find any relevant difference between CISC and RISC-V on the internet.
Matei
  • 372
  • 1
  • 8
  • 21
6
votes
1 answer

What is the point of SSE2 instructions such as orpd?

The orpd instruction is a "bitwise logical OR of packed double precision floating point values". Doesn't this do exactly the same thing as por ("bitwise logical OR")? If so, what's the point of having it?
tbodt
  • 16,609
  • 6
  • 58
  • 83
6
votes
2 answers

Why does JALR encode the LSB of the offset?

We know that jal specifies a 21-bit offset. However, it does not encode a 21-bit offset but a 20-bit one. The reason is that the least significant bit of an address is always zero because the smallest possible RISC-V instruction is 2 bytes, so this…
Lui
  • 153
  • 5
6
votes
1 answer

What does the Streaming stand for in Streaming SIMD Extensions (SSE)?

I've looked everywhere and I still can't figure it out. I know of two associations you can make with streams: Wrappers for backing data stores meant as an abstraction layer between consumers and suppliers Data becoming available with time, not all…
David Cian
  • 541
  • 1
  • 6
  • 16
6
votes
1 answer

Is it worse in any aspect to use the CMPXCHG instruction on an 8-bit field than on a 32-bit field?

I'd like to ask if using a CMPXCHG instruction on an 8-bit memory field would be worse in any aspect than using it on a 32-bit field. I'm using C11 stdatomic.h to implement a couple of synchronization methods.
Dewr
  • 404
  • 4
  • 13
6
votes
1 answer

Why is the method of im2col with GEMM is more efficient than the method of direction implementation with SIMD in CNN

The convolutional layers are most computationally intense parts of Convolutional neural networks (CNNs).Currently the common approach to impement convolutional layers is to expand the image into a column matrix(im2col) and perform and perform…
Jogging Song
  • 573
  • 6
  • 28
6
votes
1 answer

Most recent processor without support of SSSE3 instructions?

Are there any still-relevant CPUs (Intel/AMD/Atom) which don't support SSSE3 instructions? What's the most recent CPU without SSSE3?
bholanath
  • 1,699
  • 1
  • 22
  • 40
6
votes
1 answer

Why does AES in SSE not provide full function?

The Rijndael key schedule procedure involves RotWord, SubWord, and XOR, which are all supported by _mm_aeskeygenassist_si128: X3[31:0] ← SRC [127: 96]; X2[31:0] ← SRC [95: 64]; X1[31:0] ← SRC [63: 32]; X0[31:0] ← SRC [31: 0]; RCON[31:0] ←…
xtt
  • 857
  • 1
  • 8
  • 24
6
votes
1 answer

Why did RV64 introduce new opcodes for 32-bit operations instead of the 64-bit ones

While going through the RISC-V Specification I've noticed that the 64-bit version differs from the 32-bit one in the fact, that it Widened the registers to 64-bit Changed the instructions to act on the whole 64-bit range. Added new instruction to…
sannaj
  • 360
  • 2
  • 8
1 2 3
…
49 50