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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Guest VM - Exit

For the below series of instructions, is an exit possible? Which instruction can potentially cause an exit and which kind of exit? What'd be the reason for the particular type of exit? da3bd : da3bd: 4c 33 1c 24 xor …
rish
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Is CMPS a valid ARM/THUMB instruction?

I know that the CMP instruction updates the condition flags. In some material from my university, I have seen a CMPS instruction. It seems pretty senseless to me, as the condition flags are set anyways (I guess they are trying to confuse us...). I…
Fabian
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What instruction set would be easiest to implement on a homemade ALU?

I'm designing a basic 8 or 16 bit computer (haven't really decided yet) using eeprom chips, sram, and an ALU made (mostly) out of individual transistors on a PCB using cmos logic that I already have partially designed and tested. And I thought it…
Tristan367
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How to detect AVX2 support using gcc

I need to detect AVX2 support in my code take decisions accordingly. I am aware of two methods - __builtin_cpu_supports("avx2") and #if defined(__AVX2__). Now the issue is one returns true and another false. The test code is as follows - int…
Atharva Dubey
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mips-g++-5.4 listing bnez skips div instruction

I'm trying to understand why mips-g++ compiles a simple division subroutine where it skips the actual div instruction with a bnez v0, (pseudo inst for bne). My understanding is that if the divisor is zero it makes sense to skip div and trap or…
Shashank Hegde
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What type of ARMv8 instructions are LSL, LSR, ASR & ROR?

I'm learning the basics of Armv8 and am answering a homework problem asking to categorize each of the instructions into a specific type. Data processing instructions include: AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, TST, TEQ, CMP, CMN, ORR, MOV, BIC…
MFerguson
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Do RISC processors not have backward compatibility?

I'm reading a textbook which says: RISC processors have done very well in the market for embedded processors, controlling such systems as cellular telephones, automobile brakes, and Internet appliances. In these applications, saving on cost and…
user11224591
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Illegal Instruction with mm_cmpeq_epi8_mask

Im trying to run code similar to the following #include void foo() { __m128i a = _mm_set_epi8 (0,0,6,5,4,3,2,1,8,7,6,5,4,3,2,1); __m128i b = _mm_set_epi8 (0,0,0,0,0,0,0,1,8,7,6,5,4,3,2,1); __mmask16 m =…
tarashir342
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How to set the memory adress for an instruction in MIPS?

Normally, the SPIM simulator itself allocates an address to the instructions in a program. Is there some way to manually choose where to store a particular instruction?
Mohit Aggarwal
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why logical"NOT" the condition in if statement in assembly?

I'm learning assembly and a textbook shows an example of condition control: I don't understand why x>=y is used in line 3, why not just follow the logic and use x
user9623401
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The address of the "call" instruction's location

I think "call" instruction is kind of "jump" instruction. "jump" instruction have the address where to go. And "call" instruction either should have a target address. But when I disassemble the binary, "call" instruction only have a lable of target…
Joffrey
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which c code will gets changed to rlwinm power PC assembly instruciton

which c code will gets changed to rlwinm power PC assembly instruciton?? This is the snapshot of objdump.. if(!pool || pool->maxPoolSize > SEQ_MODULUS ) /* Invalid mask or pointer is null */ 29ccc: 41 82 00 dc beq- 29da8…
user2185454
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Can a build of OS kernel run both on x86 and ARM?

I mean: This build(including both x86 and ARM architecture drivers) can run on an x86 computer, and can run on an other ARM device. I know that right now, there is no such CPU that supports both instruction sets. But in theory, will it come true?…
little白
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What is the difference in load and move in assembly code?

Beginner at assembly code but I'm a bit confused between the usage of move and load, being: move ra rd load ra rd load ra (rd) from what I've read, move ra rd copies the value from RD to RA, load ra rd copies the value in RD from memory to RA,…
rabbitfufu
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Different processors have different assembly language code then which syntax to be used to solve questions in competitive exams

Mov dst,scr// in ARM PROCESSOR Mov scr,dst // in intel processor scr=source Dst= destination
Prabha
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