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I know that the CMP instruction updates the condition flags. In some material from my university, I have seen a CMPS instruction. It seems pretty senseless to me, as the condition flags are set anyways (I guess they are trying to confuse us...). I was wondering if CMPS is even a valid instruction, i.e. whether a standard ARM assembler accepts it?

I could not find anything about such an instruction online. It's not mentioned here and this online assembler/emulator does not accept it either.

Thanks in advance

Fabian
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    Probably a mistake. – Nate Eldredge Jul 22 '21 at 03:54
  • did you look at the actual arm documentation? – old_timer Jul 22 '21 at 23:34
  • @old_timer According to this "official" ARM Greencard https://developer.arm.com/documentation/qrc0001/m/ there is no such instruction. – Fabian Jul 24 '21 at 00:42
  • That is a quick reference manual, you have to be careful with arm they have documents like that that are misleading and sometimes incorrect (not due to bugs in the doc, just convey the information incorrectly when talking about the whole of their product line, the programmers reference manuals are a good example of this). The architectural reference manual for the core is the correct document assuming no bugs in the document (which all documents have bugs). – old_timer Jul 24 '21 at 07:44
  • Your question is specific to an assembly language mnemonic, which is specific to an assembly language tool (the assembler) and not the target (one of the arm instruction sets). It is trivial to create an assembly language for the arm instruction set that includes a CMPS instruction, can simply encode it as the CMP instruction for that arm instruction set and one can easily say there is a CMPS instruction for ARM. There only needs to exist one assembler in the world for this to be a true statement. – old_timer Jul 24 '21 at 07:46
  • No reason whatsoever that the assembly language even includes the CMP mnemonic, could use PICKLE or ORANGE instead so long as it properly encodes the desired instruction for that mnemonic/syntax, it is a valid assembler for that target. Might not be very popular, but it is still an arm assembly language for an arm processor. Arm has produced and acquired a number of tools over time, with not completely compatible assembly langauges, so when asking an assembly language question you must specify the assembly language (tool and version) if it is an instruction set question then ask differently – old_timer Jul 24 '21 at 07:52
  • Arm has something like 7 thumb instruction sets. Which one were you asking about? – old_timer Jul 24 '21 at 07:53
  • Or were you asking an assembly language question? And in that case which tool and version were you asking about? – old_timer Jul 24 '21 at 07:54
  • Note that there are disassemblers too and in the case of gnu as a good example even though both are part of binutils the assembler and the disassembler can produce different mnemonics, in particular for arm thumb instructions. No reason whatsoever that the disassembler has to conform to any assembly language from an assembler it can do its own thing too. – old_timer Jul 24 '21 at 07:56

2 Answers2

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You are right in every aspect, and cmps isn't even a valid instruction.

Jake 'Alquimista' LEE
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  • gnu assembler supports cmps for arm thumb. – old_timer Jul 24 '21 at 08:20
  • @old_timer And what kind of liability does gnu provide? – Jake 'Alquimista' LEE Jul 25 '21 at 09:15
  • liability. most folks use the gnu tools, they are very well known, basically the world runs off of the gnu toolchain...but that is irrelevant if this was an assembly language question as there is no one "arm assembly language" even within arm. if it is an instruction set question then it is a matter of opinion since cmp is one of the alu operations and what you call it is relative to the author of the tool. arm simply calls it a compare (that changes the flags) – old_timer Jul 25 '21 at 12:44
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.thumb
add r0,r1
and r0,r1
orr r0,r1
sub r0,r1
cmp r0,r1

assemble and disassemble

arm-none-eabi-as so.s -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   1840        adds    r0, r0, r1
   2:   4008        ands    r0, r1
   4:   4308        orrs    r0, r1
   6:   1a40        subs    r0, r0, r1
   8:   4288        cmp r0, r1

Is likely why one would assume there is a cmps. It is not a bad assumption, cmp does change the flags, and for thumb the changing of flags is implied (thumb not thumb2 extensions where it is optional). Pretty obvious what would be meant by using a mnemonic like that. But you would need an assembler that accepts it:

.thumb
adds r0,r1
ands r0,r1
orrs r0,r1
subs r0,r1
cmps r0,r1

arm-none-eabi-as so.s -o so.o
so.s: Assembler messages:
so.s:3: Error: instruction not supported in Thumb16 mode -- `adds r0,r1'
so.s:4: Error: instruction not supported in Thumb16 mode -- `ands r0,r1'
so.s:5: Error: instruction not supported in Thumb16 mode -- `orrs r0,r1'
so.s:6: Error: instruction not supported in Thumb16 mode -- `subs r0,r1'
so.s:7: s suffix on comparison instruction is deprecated

Which implies at one time there was an s there for at least one assembler, meaning it was a valid mnemonic for an arm assembly language.

You need to be careful understanding the difference between an assembly language and an instruction set. Many instruction sets have many different, incompatible, assembly languages. Within the tools created by arm for their targets you will see this. x86 is well known for decades of incompatible assembly languages (nothing to do with att vs intel ordering, within each att and intel) for the same instruction set. But there are many, not as bad as x86, incompatible, assembly languages for the same ARM instruction sets. As easily demonstrated above with an extremely popular tool. It supports two incompatible assembly languages within itself for arm thumb.

.thumb
cmps r0,r1

assemble and disassemble

arm-none-eabi-as so.s -o so.o
so.s: Assembler messages:
so.s:3: s suffix on comparison instruction is deprecated
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   4288        cmp r0, r1

So the answer is clearly yes, there is a CMPS instruction for ARM/thumb. Your university materials were correct.

old_timer
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  • That a toolchain that even refuses to give any kind of liability once used to implement a logically flawed mnemonic doesn't mean it to be a valid instruction. No, there never has been a `cmps` in ARM's book. And it's ARM ISA for every kind of reasons. – Jake 'Alquimista' LEE Jul 25 '21 at 09:13
  • cmp is assembly language syntax, and arms book is written for one of arms tools. please do not confuse the two, they are completely separate things. every other toolchain could easily write a document as well with their assembly language. – old_timer Jul 25 '21 at 12:47
  • liability of the tools is completely irrelevant, arms documents continue to have errors in them and always will, you are claiming that they will take responsibily for the damage a product causes as a result of their bugs? please go re-read their license agreements...gnu toolchains run the world, nobody comes remotely close, which means they are the best tested, most reliable, least risk. – old_timer Jul 25 '21 at 12:49
  • it is not remotely a flawed mnemonic as I clearly demonstrated, it is the natural option for that instruction. one of arms largest corporate mistakes was the unified syntax, had the not done that their world would be better. but we are in this x86 like world now, arms online documentation (other than the arm arms) is messed up as a result, confusing and incorrect, etc. but that is how assembly languages go, arm could have been better but they chose not to be. – old_timer Jul 25 '21 at 12:51
  • Everybody could modify GNU toolchains and change `cmp` to something like `xyz`. Would `xyz` be a valid instruction then? `cmps` is definitely logically flawed since the four CPSR related instructions `cmp`, `cmn`, `tst`, and `teq` don't have a destination operand. Hence their sole purpose is to update the CPSR, and ARM's documents clearly state that the s suffix isn't an option for them. BTW, GCC sucks. – Jake 'Alquimista' LEE Jul 25 '21 at 19:42