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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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How To generate hex files in RISC V?

I am trying to verify the RISC-V DUT with 32bit integer set instruction which is available at https://github.com/ucb-bar/vscale they have their inputs stored in memory as a hex file @ vscale/src/test/inputs/ ( from the above link). I would like to…
murari Venki
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Do the Airmont cores on Knight's Landing Xeon Phi's support SIMD instructions?

According to the source of the Wikipedia page on the Knight's Landing chip, it has Airmont cores. According to this page, those cores support SSE4.2 instructions, that is, SIMD instructions on SIMD registers. Is that really the case? If so, what's…
einpoklum
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ARM assembly: Basic usage of the MOV instruction

How to load the number 0xEFFFFFF2 to a register in ARM. What will be the rot in this? MVN r0, #2D1 Is this instruction valid?
Umang Okate
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Does expanding the MIPS instruction set increase the opcode?

For a 32-bit MIPS, an R-type instruction looks like this: Say that we expanded the MIPS instruction set to contain four times as many instructions. Would the opcode increase from 6-bits to 8-bits? Some sources say that the opcode would increase,…
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How to tell if Nvidia GPU cores are 32/64 bit processors

Is there a Linux/windows command that shows the type of the processor in an Nvidia GPU? I am not talking about the operating system nor the CPU type. I am asking about the processors (cores) in the GPU itself. At the end of the day, they are…
caesar
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Transpiling to C vs C++ : range of CPU instructions

I am considering the question of transpiling a language (home-grown DSL) to C vs to C++. I haven't done any 'native' programming for over 15 years, so I want to check my assumptions. Am I right into assuming that transpiling to the newest C++…
Sebastien Diot
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Factors in designing Instruction set Arcitecture

What are the two majors factors to be considered while designing Instruction Set Architecture ? I know what ISA is . But What are the factors to be considered? I already reviewed Wikipedia but it doesn't help much. I found this as design issues for…
Efrain Sanjay Adhikary
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Can't Compile for MIPS or ATOM with gcc

Using the following commands, I am trying to compile to assembly, in different ISAs gcc -S -march=atom -o mainAtom.s main.c But This still generates a x86 assembly format. gcc -S -march=mips32 -o mainMIPS.s main.c But i get the following…
Makan
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68000 Assembly: Multiplying gives a weird result

I have a question regarding the MULU instruction. One thing I've noticed is that suppose I have the value 000FFFFF in a data register. And then suppose I want to put in another F so that it contains 00FFFFFF. What I usually do is multiply the data…
Karim O.
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java concurrency - Is Instruction Level Parallelism(ILP) used underhood

Concurrency in Java or some similar languages is achieved through threads or task level parallelism. But under the hood does the hardware or run time also use ILP to achieve best performance. Little further elaboration: In a multi core processor…
samshers
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what do we mean with IPC performance

I saw material illustrating a 6% core single thread IPC performance increase from one generation of some hardware to the next. Does it mean that the number of instructions per cycle increases by 6%? What is exactly IPC performance?
kiriloff
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MIPS ADDIU confusion

I am doing an assignment on single cycle MIPS processor and I am a little confused on the addiu instruction. On this website, as my reference the author states that the immediate will be sign extened Description: Adds a register and a…
Sugihara
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MIPS, ADDIU out of range in PCSPIM

I have the follow instruction, and I don't understand why the PCSPIM is giving me the following warning: spim:(parser) immediate value (61440) out of rainge (-32768..32767) on line 88 of file addiu $a, $zero, 0xF000 ^ I…
Sugihara
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Is the LISA language object oriented?

I came across some code in the LISA language while working on an ARM based project. The code look much similar like a mix of VHDL and C++. I tried to google out to get an introduction to the language. I couldn't find much help.If some one has good…
achoora
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Can I read a valid signal from an output pin of GPIO?

According to Wikipedia: GPIO capabilities may include: GPIO pins can be configured to be input or output GPIO pins can be enabled/disabled Input values are readable (typically high=1, low=0) Output values are writable/readable To my…
xmllmx
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