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I am trying to verify the RISC-V DUT with 32bit integer set instruction which is available at https://github.com/ucb-bar/vscale they have their inputs stored in memory as a hex file @ vscale/src/test/inputs/ ( from the above link). I would like to verify my set of instructions for which i need them to be in the hex format . For example my set of instructions are ( just mentioning briefly) ADD SW LW SUB

I would like to convert these set of instructions in hex format so that I can verify its functionality. Could anyone help me out on how to go about .... would be really helpful.

Jonas
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murari Venki
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2 Answers2

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vscale/src/test/inputs have several hex inputs with similar format: 32 hex chars per line (16 bytes, 4 of 4-byte words) and 8192 lines. For example: https://github.com/ucb-bar/vscale/blob/master/src/test/inputs/rv32ui-p-add.hex

000000000000000000010101464c457f
00000034000001000000000100f30002
00280001002000340001000000000d04
00000000000000000000000100020005
00000005000007500000075000000000
...

Such files are loaded by testbench module in verilog with $readmemh function: https://github.com/ucb-bar/vscale/blob/master/src/test/verilog/vscale_hex_tb.v

module vscale_hex_tb();

   localparam hexfile_words = 8192;
...
   initial begin
      $value$plusargs("max-cycles=%d", max_cycles);
      $value$plusargs("loadmem=%s", loadmem);
      $value$plusargs("vpdfile=%s", vpdfile);
      if (loadmem) begin
         $readmemh(loadmem, hexfile);
         for (i = 0; i < hexfile_words; i = i + 1) begin
            for (j = 0; j < 4; j = j + 1) begin
               DUT.hasti_mem.mem[4*i+j] = hexfile[i][32*j+:32];
            end
         end
      end
      $vcdplusfile(vpdfile);
      $vcdpluson();
      // $vcdplusmemon();
      #100 reset = 0;
   end // initial begin

The $readmemh is documented in http://verilog.renerta.com/mobile/source/vrg00016.htm http://fullchipdesign.com/readmemh.htm

.. $readmemh reads hexadecimal data. Data has to exist in a text file. White space is allowed to improve readability, as well as comments in both single line and block. The numbers have to be stored as ... hexadecimal values. The basic form of a memory file contains numbers separated by new line characters that will be loaded into the memory.

The test inputs are used to initialize embedded memory DUT.hasti_mem.mem.

To work with such files you should know the memory map used in this testbench. Some parts of the memory may be not the instructions, but data and some initialization vectors. If you want to disassemble some of files, convert hex into binary (there are parsers for perl or you can write converter in other language or use verilog's $writememb to convert). Then add header of any binary format supported by your riscv disassembler, like elf for riscv objdump, or no any header for radare2 (https://github.com/radare/radare2) with riscv support.

osgx
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  • Hello OSGX , I really appreciate your help in this. – murari Venki Apr 17 '17 at 18:25
  • Hello OSGX , I really appreciate your help in this.I am unable to convert my assembly code to hex . i followed the isa manual https://riscv.org/specifications/ page 54 to understand the format of each set of instructions .ie load store add and subtract . How would i get the rs2,rs1,rd and imm[11:0] for the instructions in order to form my instruction.could u plz help me out on how do i form my instruction . – murari Venki Apr 17 '17 at 18:33
  • Ur help is needed.. would appreciate if you could respond immediately – murari Venki Apr 17 '17 at 18:49
  • murari, I can't respond in immediate time. What was your instruction? Do you know concept of bit and [byte](https://simple.wikipedia.org/wiki/Byte)? Of [hex numerical system](https://simple.wikipedia.org/wiki/Hexadecimal_numeral_system)? 1 byte is 8 bits, each bit is either 0 or 1 (and compact way to record byte is 3 octal digits or two hex digits like 0x5f). And 4 bytes form normal length instruction, which consist of 32 bits in total. Page 50 of linked "Volume I: RISC-V User-Level ISA V2.1" lists fields as bit offsets like [31:0] = from bit number 0 to bit number 31. rs1 is bits [19:15] – osgx Apr 17 '17 at 22:26
  • hello @OSGX could u explain how the vscale dut works briefly with the hex file....and also do u have any documentation of zscale available online – murari Venki May 08 '17 at 00:57
  • murari, as for many open-source projects there is the best and the only documentation: the source code. vScale project is now deprecated; try `spike` and `qemu` for learning RISC-V. After reset at #100 from th (src/test) core will run command with PC = h200 - https://github.com/ucb-bar/vscale/blob/master/src/main/verilog/vscale_pipeline.v#L207. Convert hex to binary and use radare2-riscv or riscv's objdump -D to disassemble. If you need docs about verilog th, meaning of # or how to convert hex to binary - vscale is wrong point of start to you. Try some https://inst.eecs.berkeley.edu/~cs250/ – osgx May 08 '17 at 01:39
  • thanks a lot @OSGX ... I understand it has been deprecated but i am already working on v-scale could u help me out with some documentation on vscale – murari Venki May 08 '17 at 02:25
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I need the same job and find the way. I am sharing that maybe others can benefit. First, you should have riscv-gnu-toolchain to make the compilation and decompilation process. It can be found here. The instructions that you mentioned are assembly. So, you can compile by riscv64-unknown-elf-as and disassemble by riscv64-unknown-elf-objdump. The instructions used to get hex are below.

omerguzel@omerguzel-HP:~/temp$ ls
code
omerguzel@omerguzel-HP:~/temp$ cat code
addi x1,x2,123
nop
xor x3,x2,x1
omerguzel@omerguzel-HP:~/temp$ /opt/riscv/bin/riscv64-unknown-elf-as code
omerguzel@omerguzel-HP:~/temp$ /opt/riscv/bin/riscv64-unknown-elf-objdump -D --section .text a.out 

a.out:     file format elf64-littleriscv


Disassembly of section .text:

0000000000000000 <.text>:
   0:   07b10093            add ra,sp,123
   4:   00000013            nop
   8:   001141b3            xor gp,sp,ra
omerguzel@omerguzel-HP:~/temp$ 

you can extract the hex part yourself by using scripts. **

Second Method:

** The other way is implemented by using other compiler tools. The commands are below.

omerguzel@omerguzel-HP:~/temp$ ls
code
omerguzel@omerguzel-HP:~/temp$ cat code
addi x1,x2,123
nop
xor x3,x2,x1
nop
omerguzel@omerguzel-HP:~/temp$ /opt/riscv/bin/riscv64-unknown-elf-as code
omerguzel@omerguzel-HP:~/temp$ /opt/riscv/bin/riscv64-unknown-elf-objcopy -O binary a.out a.bin --strip-debug
omerguzel@omerguzel-HP:~/temp$ od -t x4 -An -w4 -v a.bin 
 07b10093
 00000013
 001141b3
 00000013
omerguzel@omerguzel-HP:~/temp$