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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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What is ACTUALLY happening with parenthesis '()' in Clojure?

I'm looking for the technical answer answer here. How is Clojure interpreting these symbols? My current working understanding is that the opening paren '(' is a kind of call that calls the succeeding operator on the operands while the closing paren…
Sirgeorge
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Intel Reference Specification Questions

I'm looking at the ADD instruction, and there are so many things I don't have an idea what they mean. The gaps I have are. In the Opcode column what is /0 and /r? I understand the number is the opcode in hex. The ib/iw/id is byte/word/doubleword.…
christopher clark
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Why do we need both hardware support and software instructions for invalidating cache?

Looking at Arm as an example, it has hardware support for automatic cache invalidation as explained in this URL: https://developer.arm.com/documentation/den0024/a/Multi-core-processors/Multi-core-cache-coherency-within-a-cluster It also has software…
Dan
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What happens to a program that contains certain instructions that are not supported by the cpu in question?

Say for example in the case of x86-64 you have a program that makes use of avx-512 instructions or any other special purpose instruction, and the cpu in question does not support the instruction at the low level such as a haswell based cpu, how does…
Deank
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Why do some arithmetic instructions have a signed/unsigned variant and some don't

Assume we have: a = 0b11111001; b = 0b11110011; If we do Addition and Multiplication on paper with hand we get this result, we don't care if its signed or not: a + b = 111101100 a * b = 1110110001011011 I know that Multiplication doubles the width…
Dan
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Custom Instruction Sets

I recently saw a video that explains how to make a Custom Instruction Set (just the concept ... how it would work). This video was part of a series that in total would have 3 videos: "How to make a Custom Instruction Set", "How to make an Assembler…
Miguel Carvalho
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Instruction set simulator(SystemC) for MIPS architecture

Does anybody know if there is a open source MIPS instruction set simulator (in C++ or SystemC preferably)? I googled dozens of links and there is just no open ISS of MIPS cpu. Then only ones I know for now is Plasma CPU, which implements only a…
lukmac
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micro-benchmark to study the latency of movdir64b instruction

I want to study the latency of instruction movdir64b on a system which supports this instruction. How can I write a simple micro-benchmark to accomplish this? Note: MOVDIR64B reads 64-bytes from the source memory address and performs a 64-byte…
jhagk
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Length Disassembler And Missing Extensions

Is it possible for a Length Disassembler to correctly identify the size of an instruction without supporting extensions like VEX/EVEX/MVEX/XOP prefix'd instructions? I am asking because I have written a basic Length Disassembler, but it only…
Carol Victor
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What value is popped in the last line listed below?

The code below is contained in a FAT16 boot sector at offset 0x3E of the 512 byte sector. At boot time the sector is loaded to memory at location 0:0x7C00. The first three bytes of the sector are: EB 3C 90 which translate to the following jump…
bilsch01
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Are precompiled headers CPU architectures independent?

I learned that a compilation process makes source codes into machine codes so that the output machine codes are CPU architecture-specific. And precompiled headers are precompiled. Then how can a computer with an arbitrary CPU (and its architecture)…
WindBag
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character encoding of a computer

"A character literal can be implicitly converted to its integer value in the character set of the machine on which the C++ program is on" ---from Bjarne Stroustrup's "The C++ Programming Language" book. Fourth edition page 143 How can a physical…
shrekish
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What do modern GPUs not have?

There was a time when the difference between a CPU and GPU was very clear, but it has become increasingly blurred over the years both from the former side (SIMD vector instructions) and even more from the latter, to the point where not only are…
rwallace
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VM Instructions If an exit is possible?

bebc : mov 3423441(%rip),%r11 xor (%rsp),%r11 mov %rdx,%r8 mov %rcx,%r9 test %r8,%r8 jne bee3 mov $0x6c16,%rdi mov $0xc0f4,%rax vmwrite %rax,%rdi pushf For the above instruction, which instruction can…
ABC
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NASM assign values

i have a tiny question regarding to the following statement. Assume rax and rbx are pointing towards a valid memory address. mov byte [rax], [rbx] Why isn't that statement valid?
Metalhead
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