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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Why mcyclecfg and minstretcfg is needed?

In RISC-V, new CSRs are planning to be added. This is the documentation on Github Page. It is addressed to two problems below. • It introduces unpredictable noise to the counter values observed by the user. • It leaks information about privileged…
Ömer GÜZEL
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x86 LEA instruction doing ambiguous things

Here's the C code: int baz(int a, int b) { return a * 11; } That is compiled to the following set of assembly instructions (with -O2 flag): baz(int, int): lea eax, [rdi+rdi*4] lea eax, [rdi+rax*2] ret The lea…
Ka Kkoi
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How does the processor distinguish between multiple possible instructions for a stream of binary?

According to this hex to instruction chart, it mentions that E9 maps to the jump instruction, and the DE instruction maps to the add instruction. But, it also mentions that DEE9 maps to the "subtract and pop" instruction. So, when the processor…
declspecl
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Transform a stack using Java Virtual Machine Instruction Set

I need to transform 654321 into 654321321, using only DUP2_X1, POP, DUP_X2, POP2. I have a really difficult time with the DUP. Can anyone help? I tried to go like this: 654321 DUP2_X1 654654321, then POP goes to 65465432, then DUP_X2 we'd have…
Alex
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Systematic way to decide release date of specific Intel CPU features

I am recently developing a hypervisor. The Intel SDM lists a lot of VMX related CPU features, like "use MSR bitmaps", "virtualize APIC accesses", etc. Though I want to use these features, I would like to make sure my hypervisor can run on reasonably…
Eric Stdlib
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AND vs SUB when converting lowercase to uppercase in assembly

I was wondering why you would use the and instruction instead of the sub instruction when converting lowercase ASCII characters to uppercase ones. mov dx, 'a' sub dx, 32 vs mov dx, 'a' and dx, 11011111b
Markian
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"error: operation size not specified" on push operation. Assembly x86

I'm trying to make a simple x86 program that reverses a string, in this case: "ciao". section .data msg db "ciao" len equ $ - msg section .text global _start _start: lea eax, [msg] mov ebx, len add eax,…
Patientes
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Can a processor have same opcode for different sets of instructions?

I have a processor. Some instruction sets are AND, ADD, ANDI, ADDI. These looks like same but they are not. Can I assign same opcode for looks like same instructions sets as follows screen shot: or sixth bit is enough to differentiate them? In…
doqukan
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Why there are many instructions with zero destination that not affectting the hardware in RISC-V ISA?

The first register is hardware zero in RISC-V ISA. It is used in many cases such as calling zero to another register, and jumping but not storing the address, etc. However, there are many possibilities that don't change the hardware when the…
Ömer GÜZEL
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Orthogonality of Instruction Set Architecture

I am studying the difference between CISC and RISC recently, and I've encountered into the term "Orthogonality". After doing some research, my understanding so far is that there are two "axes", addressing modes & operations, which are independent of…
Calvin Lin
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Why atomic.Load64 function body simply return *ptr in Go source code ? Can't find assembly code for it

How amd64 function guarantees atomicity? https://github.com/golang/go/blob/master/src/runtime/internal/atomic/atomic_amd64.go package atomic import "unsafe" // Export some functions via linkname to assembly in sync/atomic. //go:linkname…
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What does the "b 1b" mean this arm64 assembly code?

.section ".text.boot" // Make sure the linker puts this at the start of the kernel image .global _start // Execution starts here _start: // Check processor ID is zero (executing on main core), else hang mrs x1, mpidr_el1 and …
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LEA and MOV instructions with emu8086. How can I solve these errors (invalid operand)?

I'd like to ask you why in emu8086 I have some problems with the MOV and LEA instructions. This is the code: format MZ entry code_seg:start ; set entry point stack 256 segment data_seg STR1 DB "INSERT…
Simone Sarugia
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Mutable data section?

I'm developing a virtual CPU for fun and I am currently working on the assembly part. Now I wonder if values in the .data section should be mutable or not. section .data MyGlobalVar dw 10h In the places where I reference MyGlobalVar, should I…
Klarre
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Categorization of x86 Assembly instructions

As described in this x86 Assembly Guide, x86 Assembly instruction can be divided into the following categories: Control Flow Instructions, Arithmetic and Logic Instructions and Data Movement Instructions However, if have not been able to find an…
MateMann
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