I am implementing an LLVM back-end for an accumulator-based processor. Currently, I seem stuck in the decision of how to match IR instructions correctly to the ISA.
An example could be an LLVM IR instruction: %c = add %a %b
Which would need to be printed as multiple machine instructions:
load a
add b
store c
What I've seen so far is, that it is possible to match combined LLVM IR operations into a single machine code operation ( ie. [(set i32:$dst, (add (mul i32:$src1, i32:$src2), i32:$src3))]>),but I have not been able to find a similar construct for the 'other' direction.
Currently, the solution I see is to define Pseudo instructions with patterns to match the LLVM IR and then expand them in custom C++ code. I'd rather not do this though since this would be completely circumventing the purpose of TableGen files, as well as requiring a large amount of custom code.
I have a hunch that it must be possible to specify such constructs in .td files, but I have not been able to find anything in the upstream backends.
As far as I can tell, all of the available backends in the LLVM upstream are register-register machines - I have not been able to find an LLVM backend with an implicit operand, (such as accumulator machines). If an open source implementation of such backend is available, I would greatly appreciate a link to such one.
