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Processors usually come with jmp-instructions to continue from a different fixed location and may depend on some condition. So the out-degree is two at most.

Are there any processors out there that have a single instruction that branches to one of three or more fixed locations?

Peter Cordes
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The Techel
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1 Answers1

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There are a lot of reasons to assume / guess no, but I'm not familiar with enough ISAs to give a definite no. Especially if we include historical early computers from the 50s and 60s; they often have very odd stuff compared to modern systems.

Normally you just use an indirect branch (target address in a register or from memory, or looked up from a compressed table with ARM tbb) if you need anything other than taken vs. fall-through, so there's very little benefit to spending an opcode on a funky direct branch instruction with 2 non-fallthrough destinations.

Also, you'd need space in the instruction encoding for either 2 separate targets, or else some special rule like fall-through, PC + offset, PC + offset*2 (i.e. jump twice as far forwards or backwards). Using it would require laying out code with targets at specific offsets. You do sometimes make a table of fixed-size blocks of instructions and compute an offset into it (instead of looking up an address from a table of addresses), but having an instruction that forced you to do that sounds unlikely.

The condition itself could be a register being - / 0 / + as a 3-way condition, or FLAGS being less-than, equal, or greater-than. Or something else.

So it sounds very unlikely, and a complication to branch-prediction (unless you just treat it as indirect, in which case why bother).

But I wouldn't be shocked if there's some combination of conditions that make it make sense on some ISA. Maybe if there's a special-case handler address in some special register, and the normal case involves taken or fall-through?

But if we allow one of the target addresses to come from a register or other internal state, any branch that can fault would count. Consider a hypothetical ISA with a compare-and-branch on memory, like Intel with macro-fused cmp [rdi], eax / jne rel32 which decodes to a single internal uop.

Then the possible targets are:

  • fall-through to RIP
  • taken to RIP+rel32
  • #PF fault to the page-fault handler address (loaded from memory on x86-64).
Peter Cordes
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  • Yes, such design choice wouldn't be of great benefit, but maybe there's some obscure architecture (There are quite a bunch of them). I haven't heard of tbb yet, but it seems the destination location is not fixed. – The Techel Jul 31 '20 at 16:46
  • @TheTechel: Yes, ARM `tbb` is just a table lookup + indirect branch. I meant to include a link, did that now. Are you including fault handlers? That's a kind of implicit 3rd destination for many instructions. But branch prediction is still going to assume that things won't fault because it's normally rare enough. You want to optimize for the fast case instead. – Peter Cordes Jul 31 '20 at 16:55