Highest Voted 'digital-logic' Questions

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How to tell if an integer is signed or not?

How can I/computer tell if binary numbers are signed or unsigned integers? Eg the binary number 1000 0001 can both be interpreted as -128, if signed, and 129, if unsigned. One advantage of using unsigned integers in languages like C (as I…

binary digital-logic

asked Oct 13 '16 at 15:49

user3675996

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1 answer

151 as an 8-bit signed binary number

Converting base 10 to base 2 n = 8 A= 49 B= 151 By doing so 49 is 00110001 and -49 would be 11001111. I am having problems with finding 151 and -151 because after the conversion it is already an 8-bit number. 151 is 10010111, but in signed binary…

binary signed digital-logic 8-bit

asked Sep 13 '16 at 02:17

Rachel Dao

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Booths multiplication algorithm extra bit at LSB

I have a confusion about the booth's multiplication algorithm. suppose we want to multiply two binary numbers A ( 7 bits) and B (7 bits) . A= 00101011 (Multiplicand) B= 00001100 (Multiplier) initial product =00000000000000 now in the next step,…

algorithm multiplication digital-logic

asked Aug 05 '16 at 13:35

user6663837

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Flip-flop and latch inferring dilemma

Could someone explain to me why a latch would be inferred instead of a flip-flop? always_ff @ (posedge clk, negedge rst) begin if (!rst) a <= '0; end Shouldn't the fact that the always block is sensitive to a signal edge be enough to infer a…

verilog hardware digital-logic flip-flop digital-design

asked Jun 01 '16 at 14:22

evilpascal

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VHDL Why is state S0 active when it isn't supposed to be?

I'm having some trouble with this piece of code. It seems that state S0 is always active, even when it is not supposed to be. It appears that the output of this state is inverted(active when it is supposed to be disabled). Any ideas? Print of the…

vhdl fpga intel-fpga quartus digital-logic

asked May 19 '16 at 23:12

Paulo Gil

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Sorting the bits of a 32-bit vector. Verilog

I need to do a design that sorts the bits of a 32-bit vector(not sure if it's called vector) like this: 1010010101010 => 00000001111111 I must have a 32-bit parallel in and a serial out and it must be combinational. I tried something like…

sorting verilog digital-logic

asked May 14 '16 at 20:21

Alex Mihai

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Index constraint violation in vhdl

I've a problem with the simulation of my code. I have an asynchronous FIFO that is composed by a dual port memory. The write are performed synchronous to the writing clock, the read are performed providing the address of the location I want to read.…

vhdl simulation fifo digital-logic

asked Apr 21 '16 at 11:07

haster8558

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how to create a T- flip flop in ladder logic?

This is a bridge application where I need to alternate between 2 motors. Therefore, if you use motor 1 in the first raise/lower bridge cycle, you need to use motor 2 for the second bridge cycle. When the bridge is fully seated, there is a digital…

plc digital-logic flip-flop

asked Apr 13 '16 at 16:03

Dhananjay Ramesh

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sum of minterm vs product of maxterm

Given the following Boolean expression of F(A,B,C): F(A,B,C) = A' + B + C' Which of the following statements is/are true about the above expression? (i) It is an SOP expression (ii) It is a POS expression (iii) It is a sum-of-minterms…

boolean-logic boolean-expression digital-logic karnaugh-map

asked Mar 07 '16 at 07:43

weejing

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Static Hazard 1 and One Circuit Problems?

I read about Static Hazard. We know Static 1-hazard is: Input change causes output to go from 1 to 0 to 1. My note covers a Circuit as follows: My notes says: When B=C=D=1, for any changes in A values, it's probable to have Static Hazard 1. But I…

cpu-architecture circuit digital-logic digital-design cpu-hazard

asked Feb 11 '16 at 10:18

user5912880

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3 answers

Boolean expression in SOP

I'm new to boolean expressions. I've been given the task to simplify F(w,x,y,z) = xy’ + x’z’ + wxz + wx’y by using K map. I've done it and the result is wx’+w’y’+xyz. Now I have to "Write it in a standard SOP form. You need to provide the steps…

algorithm boolean boolean-expression digital-logic boolean-algebra

asked Feb 05 '16 at 15:57

Dominik Banialis

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Implementing one-bit flags in a 32Bit ALU using Verilog

I am working on an assignment and am a little lost and don't really know how to get started. I need to implement the following flags in a 32Bit ALU: • Z ("Zero"): Set to 1 ("True") if the result of the operation is zero • N ("Negative"): Set to 1…

verilog digital-logic alu iverilog status-register

asked Dec 06 '15 at 00:35

Scruffy Nerfherder

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bit_vector bounds violation by static constant

Posting this question on SO and not EE is because I am struggling with coding/software imperfections. I am new to VHDL and going through "Free range VHDL" book. Playing around with bit_vector I found out that to access single wire in a bus syntax…

vhdl digital-logic ghdl

asked Dec 06 '15 at 00:34

hrust

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4Way Demultiplexer circuit using Verilog

I am struggling here on an assignment for my digital logic class. I have searched online for resources, but there is not much that has proven to be helpful. It seems that everyone has a different approach than what we are doing in class. There is no…

verilog digital-logic iverilog

asked Nov 29 '15 at 21:02

Scruffy Nerfherder

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Boolean expression to determine if 8-bit input is within range

Given the following in 8-bit 2s complement numbers: 11000011 = -61 (decimal) 00011111 = +31 (decimal) I am required to obtain a boolean expression of a logic circuit whose output out goes high when its 8-bit input in (also in 2s complement…

boolean-expression twos-complement digital-logic

asked Nov 21 '15 at 03:35

JTJM

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Questions tagged [digital-logic]