Sorting the bits of a 32-bit vector. Verilog

Question

I need to do a design that sorts the bits of a 32-bit vector(not sure if it's called vector) like this:

1010010101010 => 00000001111111

I must have a 32-bit parallel in and a serial out and it must be combinational.

I tried something like this:

assign c=in[0]+in[1]+in[2]+in[3]+in[4]+in[5]+in[6]+in[7]+in[8]+in[9]+in[10]+in[11]+in[12]+in[13]+in[14]+in[15]+in[16]+in[17]+in[18]+in[19]+in[20]+in[21]+in[22]+in[23]+in[24]+in[25]+in[26]+in[27]+in[28]+in[29]+in[30]+in[31];

assign out=(1<< c)-1;

But I thought I would need to do the design sequential if I count the ones.

Can you please help me do this? My head hurts from trying to understand verilog.

Your posted solution is combinational - you're not using any registers. Your critical path will be long, but it should work. — wilcroft, May 15 '16 at 02:52
I don't think you can have a serial output implemented with combinational circuit, you need a clock and register(s). — George Gkitsas, Dec 02 '16 at 16:07

score 0 · Answer 1 · answered Mar 13 '17 at 10:27

"Serial out" means 1 bit per cycle. You need a 1-bit out signal and a counter that selects one of the 32-bits of the result. Assuming your clock is called clk and your active-low reset rstn

logic[31:0] result;
logic[4:0] cnt;
assign c=in[0]+in[1]+in[2]+in[3]+in[4]+in[5]+in[6]+in[7]+in[8]+in[9]+in[10]+in[11]+in[12]+in[13]+in[14]+in[15]+in[16]+in[17]+in[18]+in[19]+in[20]+in[21]+in[22]+in[23]+in[24]+in[25]+in[26]+in[27]+in[28]+in[29]+in[30]+in[31];
assign result = (1 << c) - 1;
always_ff @(posedge clk, negedge rstn)
   if (!rstn)
       cnt <= 0;
   else
       cnt <= cnt+1;
assign out = result[cnt];

Sorting the bits of a 32-bit vector. Verilog

1 Answers1