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Questions tagged [cpu-architecture]

The hardware microarchitecture (x86, x86_64, ARM, ...) of a CPU or microcontroller.

The hardware architecture and ISA (x86, x86_64, ARM, ...) and the micro-architectural implementation of a CPU or microcontroller.

Some of the key architecture:

  • arm - 32-bit Advanced RISC Machine.
  • arm64 - 64-bit Advanced RISC Machine.
  • ia32 - 32-bit Intel Architecture.
  • mips - 32-bit Microprocessor.
  • mipsel - 64-bit Microprocessor.
  • ppc - PowerPC Architecture.
  • ppc64 - 64-bit PowerPC Architecture.

Use this tag for questions regarding features, bugs and details concerning the inner working of specific CPU architectures.

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Why is the Branch Target Buffer designed as a cache?

The BHT is not a cache and it doesn't need to be because it is okay if a mistake is made when accessing it. The BTB, however, is designed as a cache because it always has to return either a hit or a miss. Why can't the BTB make a mistake?
Ines Brager
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How to flush cache line in aarch64

How can I flush the cache line on aarch64 inside the userspace code? Just like on x86 we can use the following lib call: _mm_clflush(&array); I tried the following code: void flush(void) { asm volatile ( "MCR p15, 0, =0x0,c7, c6, 0\n"); …
xiaogw
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Why is clock cycle time the inverse of clock rate?

Im studying computer performance and I cant understand why clock cycle time = 1 / clock rate Why is this obvious?
user5345345
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What is the point of on-chip hardware accelerators, instead of that functionality being added as an instruction to the ISA?

I get that if a specialized operation is known to be common, it makes sense to do it in hardware. But at that point, why not make it a part of the ISA so it can be even faster? Is there a benefit to making it a co-processor that communicates…
KenArrari
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Difference between high memory and high memory area

Can somebody please explain me the difference between the terms high memory and high memory area. I have always came across these terms. I searched a lot about these terms but still i didn't got exactly how they are different.As far as I know both…
pradeepchhetri
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Why are offset bits in the interrupt descriptor table (IDT) separated to two fields?

For the IA-32 architecture, an IDT entry has the following format: struct IDTDescr { uint16_t offset_1; // offset bits 0..15 uint16_t selector; // a code segment selector in GDT or LDT uint8_t zero; // unused, set to 0 uint8_t…
Harold H.
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Inferring value from a single cycle MIPS diagarm

so glad i've found this place, hoping to learn here from other and help if i can. my question is about understanding a single cycle MIPS: how can i know the values of 3,5 and 12? if you can, please explain it slowly so i could learn fast. additional…
javablemountain
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Could multi-cpu access memory simultaneously in common home computer?

As far as I know, in modern mult-core cpu system, different cpus share one memory bus. Does that mean only one cpu could access the memory at one moment since there are only one memory bus which could not be used by more than one cpus at a time?
choxsword
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Cache architecture in gem5 simulator

How can I modify the cache architecture in the gem5 simulator? I want to be able to configure the cache so that it is used differently (either set-associative or fully associative) depending on a certain execution mode? I am new to gem5 and still…
g.dessouky
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Memory barriers: A hardware view for software hackers - invalidate queues

Even though Memory barriers: a hardware view for software hackers book is considered extremely old (by it's author, seems like Paul himself answered this question) I find it as an excellent helper to build a mental model around memory…
Artem Konovalenkov
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RISC V manual confusion: instruction format VS immediate format

I have some question related the RISC V manual It has different types of instruction encoding such as R-type,I-type. Just like the MIPS encoding. * R-type 31 25 24 20 19 15 14 12 11 7 6 0 …
Billy
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What memory access architecture has an i9 processor?

What memory access architecture has and i9 processor (UMA ,NUMA OR CC-NUMA)? Is it different from previous processors like i7?
bembas
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How does Out of Order execution work with conditional instructions, Ex: CMOVcc in Intel or ADDNE (Add not equal) in ARM

I know they can only correctly execute after instructions before them in Re-Order Buffer are committed. My doubt is, do modern processors hold them till they are last in ROB or do any prediction counters/structures are used even for predicting the…
Tiwari
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a specific case of data hazard( when a R-Type instruction comes after two consecutive LW )

I am designing a MIPS-like CPU with Verilog and now I'm handling data hazards. I have these instructions: Ins[0] = LW r1 r0(100) Ins[1] = LW r2 r0(101) Ins[2] = ADD r3 r2 r1 I'm using pipeline and my dataPath is something like this: I have 5…
Kamran Hosseini
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Zilog z80 I, R registers purpose

There are I and R registers in the Control section of the Z80 cpu, what is their purpose and usage?
Mikhail Veselov
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