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Questions tagged [cpu-architecture]

The hardware microarchitecture (x86, x86_64, ARM, ...) of a CPU or microcontroller.

The hardware architecture and ISA (x86, x86_64, ARM, ...) and the micro-architectural implementation of a CPU or microcontroller.

Some of the key architecture:

  • arm - 32-bit Advanced RISC Machine.
  • arm64 - 64-bit Advanced RISC Machine.
  • ia32 - 32-bit Intel Architecture.
  • mips - 32-bit Microprocessor.
  • mipsel - 64-bit Microprocessor.
  • ppc - PowerPC Architecture.
  • ppc64 - 64-bit PowerPC Architecture.

Use this tag for questions regarding features, bugs and details concerning the inner working of specific CPU architectures.

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How to test privileged x86-64 CPU instructions?

I'm trying to learn/test x86-64 privileged instructions & memory protection / management (which causes #GP exceptions in a user mode code.) At the moment I'm re-using a template device driver that I installed in a VM in a Win7 x64 client OS. After…
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Does a memory barrier acts both as a marker and as an instruction?

I have read different things about how a memory barrier works. For example, the user Johan's answer in this question says that a memory barrier is an instruction that the CPU executes. While the user Peter Cordes's comment in this question says the…
Steve
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How virtualized page table works

Reading about the virtualized page table concept, where part of the page table is put in virtual memory. Wikipedia as well as Patterson & Hennessy (5.7 elaboration in the Page Faults section) say that the reason you don't put the entire page table…
allstar
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Six stage pipelining with superscalar processor with two execution units

Need help in designing a six-stage pipelining with superscalar processor with two execution units. Six stages are Instruction Fetch (IF), Instruction Decode (ID), Read from Registers (RR), 2-cycle Execution (EX), Write back result (WB). Instructions…
Dr. Debasish Jana
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how to config linux/CPU better for large scale software running (NUMA)

I am doing performance analysis on linux for large scale programs which is memory driven(tens of Gigabytes memory). I am thinking if it's possible to config linux/hardware to be more suitable to run such kind of large programs. But I am not…
limi
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MIPS pipeline registers length (IF/ID, ID/EX, EX/MEM, MEM/WB)

I am currently studying for my Computer Architecture exam and came across a question that asks to illustrate (bit by bit i would assume) the values contained in the mips pipeline architecture after the 3rd stage of the sub (before the clock…
WiserTheBassist
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Is TLB used at all in the instruction fetching pipeline

Is a TLB used at all in the instruction fetching pipeline? Is this architecture / microarchitecture - dependent?
Kay
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Compile time architecture detection in cmake

So I have a library I'm working on that has, or will have, optimised assembly per architecture of the cpu. We're talking about optimising for nehalem, or core2, or k8 or whatever. Anyway, I've been experimenting with build systems recently and have…
user257111
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gem5 to McPAT template.xml file for 2018

I am having lots of issues trying to convert my output from gem5 simulator into a proper xml format for input to McPAT. I am using gem5 version 2.0 which is the latest version, and I am using the 2015 McPAT release. I was given a template.xml file…
mks
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Why are there different packages for the same architecture, but different OSes?

My question is rather conceptual. I noticed that there are different packages for the same architecture, like x86-64, but for different OSes. For example, RPM offers different packages for Fedora and OpenSUSE for the same x86-64 architecture:…
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Why does this block of assembly code have 2 stalls in pipeline instead of 1?

To elaborate on the main question, why does the third line perform an execution a clock cycle after Register2 has already been written back? I was thinking it should only have 1 stall in the pipeline. But I am incorrect. Is it just some quality with…
Cristian G
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How does L1, L2 and L3 cache work with multiple concurrently running processes?

I have studied the cache and how to utilise it effectively for a few years now. I know all about the hierarchy of caches, how a block of cache is fetched according to cache line, how the prefetcher detects memory access patterns and fetches memory…
Zachariah the Magnificent
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value of PMC (Performance Monitoring Counter) for L3 cache-misses is too high

I'm searching a way to estimate the number of L3 cache-misses by using 'IA32_PERFEVTSELx' and 'IA32_PMCx' MSR pair on my Linux PC with Intel CPU (Intel i7 6700 skylake). To do that, I installed a timer in the kernel and it reported the value of a…
nickeys
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Universal Gate (NOR or NAND) Operator using Only Addition and Subtraction (8 bit)

I'm constructing an implementation of Ben Eater's 8 bit computer and the claim at the end is that it will be made turing complete by adding a conditional jump instruction. If this is true, then it should be possible to execute logical operators such…
rjm27trekkie
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Why is pause() "efficient use of the CPU"?

Taking a course in Operating systems and are new to this (and C), I dont really understand a fact stated in my studying material. The program is suppose to pause execution until a kill-command is issued (ctr+c or kill from the terminal) From the…
Meltdown
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