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Questions tagged [cpu-architecture]

The hardware microarchitecture (x86, x86_64, ARM, ...) of a CPU or microcontroller.

The hardware architecture and ISA (x86, x86_64, ARM, ...) and the micro-architectural implementation of a CPU or microcontroller.

Some of the key architecture:

  • arm - 32-bit Advanced RISC Machine.
  • arm64 - 64-bit Advanced RISC Machine.
  • ia32 - 32-bit Intel Architecture.
  • mips - 32-bit Microprocessor.
  • mipsel - 64-bit Microprocessor.
  • ppc - PowerPC Architecture.
  • ppc64 - 64-bit PowerPC Architecture.

Use this tag for questions regarding features, bugs and details concerning the inner working of specific CPU architectures.

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solution to rdtsc out of order execution?

I am trying to replace clock_gettime(CLOCK_REALTIME, &ts) with rdtsc to benchmark code execution time in terms of cpu cycles rather than server time. The execution time of the bench-marking code is critical for the software. I have tried running…
Vaibhav Dixit
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Registers in the CPU of a computer

I just want to verify if the CPU itself supports names of "registers". I mean arg0 arg1 arg2... etc is at the end "names". Does the CPU support also names?! I'm not asking about the register itself, I'm asking whether the CPU supports names of the…
Ryan
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Process.GetProcesses and IsWow64Process does not return all the running processes

Im using this simple code to list all the running processes and their architecture (32bit or 64bit) on console, And it works nearly accurate but the number of processes in result is not even half of what i see in WindowsTaskManager or ProcessHacker.…
0_o
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Multicore simulation in gem5 simulator: How it works

I want to simulate multicore simulation in gem5. where each program running in each core. For that I use following command with an expectation that different program running in different threads in different cores - build/ALPHA/gem5.opt…
Moumita Das
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Precise exception

I was going through the book The Design and Implementation of the FreeBSD operating system and I came across this: This ability to restart an instruction is called a precise exception. The CPU may implement restarting by saving enough state when…
sham1810
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amd and intel programmer's model compatibility

I have read through Intel's Software Development Guide's (vol 1-3). Without doing a doing a similar read through AMD's Programming Guides (vol 1-5), I am wondering what aspects of Intel and AMD's programming model are the same. Of course, even…
Abel
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How is DMA cache coherency kept on Intel chipsets?

I was reading something a few months ago about windows chipset iterations and PCH upgrades between them and I'm pretty sure I saw something on DMA cache coherency and that it involves the home agent or QHL (Nehalem) but I can't find it now. So I ask…
Lewis Kelsey
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Do software prefetching hints disable hardware prefetcher?

The motivation of this quesion is to understand how software memory prefetching affects my program. I'm building a multi-threaded data partitioner. Each thread sequencially read over a local source array and randomly write to another local…
Amos
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How many Supported architectures should I choose while creating apk file

I have android app, size of my android apk file is 25MB. So while creating apk file I want to know how many Supported Architectures is must, in order to reduce apk size. Targeting 4.1 to 8.1 Android version.
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If CPU is a binary machine, why is it slow on bit manipulations?

I found that contrary to its binary / bi-state nature, x86 CPUs are very slow when processing binary manipulations instructions such as SHR, BT, BTR, ROL and something similar. For example, I've read it from somewhere that bit shifting / rotate…
royalfinest
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How to check if a function is calling back to itself

Let's say we have a C function funA in a library, inside funA it'll call some other functions funB, funC, .etc. It's possible that funB and funC could call funA back. So the question is: Is it possible to detect this situation just inside funA,…
Bill Randerson
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What kernel type does the RTOS eCos use?

From my research I cannot find what kernel type is being used in eCos, such as monolithic or micro-kernel. All I could find from my research is that the kernel is a real-time one or websites just describe it as the eCos kernel, does this mean it is…
Jordan
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About negate a sign-integer in mips?

I'm thinking about how to negate a signed-integer in mips32. My intuition is using definition of 2's complement like: (suppose $s0 is the number to be negated) nor $t0, $s0, $s0 ; 1's complement addiu $t0, $t0, 1 ; 2's = 1's + 1 then I realized…
Kindred
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Why the RISC instruction sets usually do not contain register to register copy instruction?

I had this question on my exam and i am confused because as far as i know that move $t0, $a0 # COPY $A0 TO $T0 in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something?
roffensive
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What happens with the IFU and the front end when an instruction is not in L1I?

Firstly, when the IFU issues a request for 16 bytes, is this interaction with the L1I modified/fixed such that when L1I receives an address from the IFU it will subsequently produce 16 bytes in succession or does the IFU have to send the addresses…
Lewis Kelsey
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