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Questions tagged [cpu-architecture]

The hardware microarchitecture (x86, x86_64, ARM, ...) of a CPU or microcontroller.

The hardware architecture and ISA (x86, x86_64, ARM, ...) and the micro-architectural implementation of a CPU or microcontroller.

Some of the key architecture:

  • arm - 32-bit Advanced RISC Machine.
  • arm64 - 64-bit Advanced RISC Machine.
  • ia32 - 32-bit Intel Architecture.
  • mips - 32-bit Microprocessor.
  • mipsel - 64-bit Microprocessor.
  • ppc - PowerPC Architecture.
  • ppc64 - 64-bit PowerPC Architecture.

Use this tag for questions regarding features, bugs and details concerning the inner working of specific CPU architectures.

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How is CPU usage calculated?

On my desktop, I have a little widget that tells me my current CPU usage. It also shows the usage for each of my two cores. I always wondered, how does the CPU calculate how much of its processing power is being used? Also, if the CPU is hung up…
Chris Laplante
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Line size of L1 and L2 caches

From a previous question on this forum, I learned that in most of the memory systems, L1 cache is a subset of the L2 cache means any entry removed from L2 is also removed from L1. So now my question is how do I determine a corresponding entry in L1…
prathmesh.kallurkar
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Why is the loop instruction slow? Couldn't Intel have implemented it efficiently?

LOOP (Intel ref manual entry) decrements ecx / rcx, and then jumps if non-zero. It's slow, but couldn't Intel have cheaply made it fast? dec/jnz already macro-fuses into a single uop on Sandybridge-family; the only difference being that that sets…
Peter Cordes
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What happened to clockless computer chips?

Several years ago, the 'next big thing' was clockless computers. The idea behind it was that without a clock, the processors would run significantly faster. That was then, this is now and I can't find any info on how it's been coming along or if…
GeoffreyF67
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What is a cache hit and a cache miss? Why would context-switching cause cache miss?

From the 11th Chapter(Performance and Scalability) and the section named Context Switching of the JCIP book: When a new thread is switched in, the data it needs is unlikely to be in the local processor cache, so a context-switch causes a flurry…
Geek
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How many CPU cycles are needed for each assembly instruction?

I heard there is Intel book online which describes the CPU cycles needed for a specific assembly instruction, but I can not find it out (after trying hard). Could anyone show me how to find CPU cycle please? Here is an example, in the below code,…
George2
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What does it mean by word size in computer?

I have tried to get a grasp of what "word" means and I have looked in the wiki and the definition is vague. So my question is what is "word size"? Is it the length of the data bus, address bus?
kofhearts
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how much memory can be accessed by a 32 bit machine?

What is meant by 32bit or 64 bit machine? It’s the processor architecture…a 32 bit machine can read and write 32bit data at a time same way with 64 bit machine…. whats the maximum memory that a 32 bit machine can access? It is 2^32=4Gb (4Gigabit =…
haris
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Aligning to cache line and knowing the cache line size

To prevent false sharing, I want to align each element of an array to a cache line. So first I need to know the size of a cache line, so I assign each element that amount of bytes. Secondly I want the start of the array to be aligned to a cache…
MetallicPriest
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How to write C/C++ code correctly when null pointer is not all bits zero

As the comp.lang.c FAQ says, there are architectures where the null pointer is not all bits zero. So the question is what actually checks the following construction: void* p = get_some_pointer(); if (!p) return; Am I comparing p with machine…
ivaigult
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After update to Xcode 5 - ld: symbol(s) not found for architecture armv7 or armv7s linker error

I just updated my iPhone 4S software to iOS 7 Beta 2 while I was in the middle of putting the final touches on a new app (Phonegap).. not a good idea! After it was done Xcode didn't detect my iPhone so I installed Xcode 5 beta. After tinkering…
barney
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Turing machine vs Von Neuman machine

Background The Von-Neumann architecture describes the stored-program computer where instructions and data are stored in memory and the machine works by changing its internal state, i.e an instruction operates on some data and modifies the data. So…
Santhosh
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How are atomic operations implemented at a hardware level?

I get that at the assembly language level instruction set architectures provide compare and swap and similar operations. However, I don't understand how the chip is able to provide these guarantees. As I imagine it, the execution of the instruction…
Alexander Duchene
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Why is x86 little endian?

A real question that I've been asking myself lately is what design choices brought about x86 being a little endian architecture instead of a big endian architecture?
bfrog
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What is the difference between x64 and IA-64?

I was on Microsoft's website and noticed two different installers, one for x64 and one for IA-64. Reference:Installing the .NET Framework 4.5, 4.5.1 My understanding is that IA-64 is a subclass of x64, so I'm curious why it would have a separate…
James Oravec
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