Formal verification with Chisel

Question

Is it possible to do formal verification with Chisel3 HDL language? If yes, is there an open-source software to do that ? I know that we can do verilog formal verification with Yosys, but with chisel ?

Answer 1

SpaceCowboy asked the same question here. And jkoening responded it: not now but maybe it will be done.

Answer 2

It's possible to use Yosys-smtbmc with some little hacks described here to «inject» formal properties in Verilog generated.

Answer 3

There is a chisel package named chisel-formal now.

import chisel3.formal._

This extends Module with trait named Formal.

class MyModule extends Module with Formal {
//...
      past(io.Mwrite, 1) (pMwrite => {
        when(io.Mwrite === true.B) {
          assert(pMwrite === false.B)
        }
      })
      cover(countreg === 10.U)
//...
}

That allow to use assert(), assume(), cover(), past(), ... functions.

Full howto is given on github repository.

Answer 4

formal verification is now integrated under chiseltest official test library.