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Questions tagged [xeon-phi]

a co-processor/accelerator from Intel

Intel Many Integrated Core Architecture or Intel MIC (pronounced Mike) is a multiprocessor computer architecture developed by Intel incorporating earlier work on the Larrabee many core architecture, the Teraflops Research Chip multicore chip research project, and the Intel Single-chip Cloud Computer multicore microprocessor.

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any ways to convert unsigned char to short based on AVX512 cpu intrinics?

I am just reading the cpu intrinic sets of AVX512 in Xeon Phi processors, but it seems that traditional data type converting method in sse doesn't work in avx512, so can I ask that are there any similar cpu set in avx512 can convert unsigned char…
pottermarkken
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How to bind my job to intel xeon phi coprocessor?

I have a server with four mic cards (mic0-mic3), and it works well. how to bind a parallel job(mic_app) to mic0, other parallel job can not run in mic0. how to detect the mic0 has been running for a parallel job(mic_app).
LEo
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Meaning of nocopy clause in Xeon Phi Programming

I'am new to Xeon Phi Programming and i'am currently trying to learn explicit offload programming ... I have been going through certain tutorials provided by intel but i couldn't properly understand the meaning of nocopy clause if any one know about…
Bharath Vemula
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convert 8-bit unsigned integer to/from float on Intel Knights Corner (KNC, Xeon Phi Gen 1)

I'm making a program for the Knights Corner (KNC) cpu to execute. It seems to have a prototype of AVX512 as its instruction set, but I could find no indication on the Intel Intrinsic Guide for conversion between various integer widths.…
user1649948
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Using vector units through threading

To use the vector units, e.g 512-bit wide for simultaneous operation on 8 double precision values, is it necessary to be single threaded and use AVX intrinsics ? If my program is not easy to vectorize, could i maybe get some of the benefit by…
danny
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Disable hardware prefetcher on Xeon Phi

Is it possible to disable hardware prefetcher on Xeon Phi preferably via programming? I want to measure the percent performance improvement provided by the hardware prefetcher for the STREAM benchmark. I do not want to change the original STREAM…
Kadir
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How to cross-compile checksum algorithm of OpenSSL for Monetdb5?

I'm trying to cross-compile the Monetdb5 (11.21.19) using the intel icc compiler in order to port Monetdb to Xeon Phi. My configure command is: ./configure CC=icc CFLAGS=-mmic --prefix=/home/xxx/monetdb/phiMonetdb --host=x86_64-intel-linux…
thierry
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OpenMP offloading tasks to Intel MIC

I am trying to offload an expensive loop in my program to Intel MIC. The part of the code is: !$omp target map(to:coor,sigma_const,clase) map(tofrom:ener1,ener2) !$omp parallel private(i,j,fdummy1,k,l,fdummy2,fdummy3,fdummy4,fdummy5,dist) !$omp do…
armando
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ICC reduction is slow and produce wrong results

I am trying to write a simple reduction code for Xeon Phi co-processor using Intel Compiler (ICC). However, my code has two problems: the first problem is that it produce wrong result and it is slower than the serial solution. I compiled the code…
Hamid_UMB
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Most efficient way to work with HUGE binary matrix?

I have a huge binary matrix, like 100000 x 100000. Reading this article http://www.cs.up.ac.za/cs/vpieterse/pub/PieterseEtAl_SAICSIT2010.pdf, I seemed to understand that the best tradeoff to memorize and work with a binary matrix is using…
Draxent
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How to compile Xeon phi patched gcc from source?

I downloaded the MPSS software stack version 3.5.2 source code from the intel website. I am trying to compile the xeon phi ported GCC (ported from GCC 4.7.0) from source and install it in a local subdirectory. However, I am getting the following…
lipak
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Possible bug in vtune on Xeon Phi

I ran vtune on a xeon phi core and obtained a CPI of 0.777 for a single threaded benchmark. However, this seems really unlikely to be true because the theoretical maximum CPI is 1.0 for a single thread. (search for "Theoretical CPI" on…
user2722716
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Applications well suited for Xeon-phi many-core architecture

From this https://software.intel.com/en-us/videos/purpose-of-the-mic-architecture I understand that applications with complex or numerous random memory access are not well suited for Intel Xeon-phi. This is because the architecture uses 61 cores and…
kiriloff
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how to build cado-nfs for intel xeon mic

I have platform radhat and icc, icpc for intel xeon mic I found that i command 'icc -mmic' as c compiler for Executing some program on intel xeon mic. (also, icpc, ... etc) So, I use 'cmake' for compiling cado-nfs When I compiled cado-nfs, I add…
wtfcj
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Installing OpenCL on XeonPhi

Because I don't have device to test so I ask this question If i use OpenCL on XeonPhi I only want install the driver and runtimes of XeonPhi (https://software.intel.com/en-us/articles/opencl-drivers), then OpenCL can run and complier code, is that…
AnNguyen
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