Stack Overflow
Stack Overflow

Questions tagged [xeon-phi]

a co-processor/accelerator from Intel

Intel Many Integrated Core Architecture or Intel MIC (pronounced Mike) is a multiprocessor computer architecture developed by Intel incorporating earlier work on the Larrabee many core architecture, the Teraflops Research Chip multicore chip research project, and the Intel Single-chip Cloud Computer multicore microprocessor.

188 questions
1
vote
1 answer

What are JKZD and JKNZD?

Looking through Zydis ( https://github.com/zyantific/zydis/blob/57be5b1d1b9dd99830b89caac928add64ad5d072/include/Zydis/Generated/EnumMnemonic.h ) mnemonics I found these: ZYDIS_MNEMONIC_JKNZD, ZYDIS_MNEMONIC_JKZD, I couldn't find these mnemonics…
Hi - I love SO
  • 615
  • 3
  • 14
1
vote
1 answer

Automatic Offloading with Intel Python 2019 and Xeon Phi (KNC)

I am currently trying to get automatic offloading working using Intel Python 2019 and a Xeon Phi X100 KNC (SC3120A) card. For testing the offloading I am trying this benchmark:…
mapf
  • 496
  • 1
  • 5
  • 21
1
vote
1 answer

What is lost in going from AVX512 on Intel Xeon Phi to AVX2 on Intel i5-8259U?

Trying to follow a course on Coursera, I tried to optimize a sample C++ code for my Intel i5-8259U CPU which I believe supports AVX2 SIMD instructions set. Now, AVX2 supplies 16 registers per core (called YMM0, YMM1, ..., YMM15) which are 256-bit…
Nanashi No Gombe
  • 510
  • 1
  • 6
  • 19
1
vote
2 answers

Hardware for python multiprocessing

I have a task where I need to run the same function on many different pandas dataframes. I load all the dataframes into a list then pass it to Pool.map using the multiprocessing module. The function code itself has been vectorized as much as…
alittlebluebug
  • 38
  • 4
1
vote
0 answers

Anaconda/IntelPython doesn't seem to offload to Xeon Ph 30

>>> import numpy >>> numpy.show_config() mkl_info: libraries = ['mkl_rt', 'pthread'] library_dirs = ['/home/steph/anaconda3/envs/intel_py/lib'] define_macros = [('SCIPY_MKL_H', None), ('HAVE_CBLAS', None)] …
svanschalkwyk
  • 26
  • 4
1
vote
0 answers

Convert array of eight bytes to eight integers

I am working with the Xeon Phi Knights Landing. I need to do a gather operation from an array of doubles. The list of indices comes from an array of chars. The gather operations are either _mm512_i32gather_pd or _mm512_i64gather_pd. As I understand…
Z boson
  • 32,619
  • 11
  • 123
  • 226
1
vote
0 answers

MCMC sampling using emcee is running extremely slow on intel xeon phi processor

So, I have the following code for MCMC for the parameters of a Gaussian process code: walkers = 250 pos_min = np.concatenate((np.array([self.initial_scale, self.initial_noise]), np.zeros(self.ndim))) pos_max =…
grok
  • 131
  • 3
1
vote
0 answers

Xeon-Phi vs. Xeon Unexplained Overhead

I am trying to run the following code with different n sizes on an Xeon Phi KNC (with 61 cores and 4T/C) and Xeon (with 2 sockets of Xeon E5-2660 v2). I am getting the timings as shown in the tables below. However, I am trying to understand why…
Gal Oren
  • 31
  • 3
1
vote
1 answer

Unexplained Xeon-Phi Overhead

I am trying to run this code with these different n sizes on an Xeon Phi KNC. I am getting the timings as shown in the table, but I have no idea why I am experiencing those fluctuations. Can you please guide me through it? Thanks in…
Gal Oren
  • 31
  • 3
1
vote
0 answers

Build OpenSSL for Intel Xeon Phi on Windows

I try build OpenSSl for Intel Xeon Phi coprocessor. So far as I understand this problem reduced to building OpenSSL for "linux-generic64" as target (this document). I have Windows10(x64) and VC2015. So I use next string for configure: /perl…
Alexander D
  • 11
  • 1
1
vote
0 answers

Architecture of IMCs(Integrated Memory Controllers) in latest Intel processors

I have been looking into Xeon architecture for a server application. I saw that Xeon supports Quad channel architecture with 3 DIMMs per channel. I have attached a page from Intel's Xeon datasheet. I got this from…
electro_sm11
  • 63
  • 2
  • 9
1
vote
1 answer

Syscfg error KNL - Error: Failed in export HII base address from SMI driver

sudo /bin/syscfg/syscfg /d biossettings "Cluster Mode" sudo /bin/syscfg/syscfg /d biossettings "Memory Mode" I tried these syscfg commands on KNL(Knights Landing) but it gives this error. No data returned from CR Error: Failed in export HII base…
Krunal
  • 7,048
  • 1
  • 18
  • 19
1
vote
1 answer

How AVX-512CD (conflict detection) differs from atomic variables access?

So I was watching this ANL Training video and they show how void Histogram ( const float* age, int* const hist, const int n, const float group_width, const int m) { const float oogw = 1.0f / group_width; // Populating the histogram. for(…
DuckQueen
  • 772
  • 10
  • 62
  • 134
1
vote
0 answers

OpenMP target (update) into

I am working with OpenMP 4.5 Accelerator Model on platform equipped with Intel Xeon Phi coprorcessors. I would like to use CPU + MIC to joint problem solving. I need use mechanism similar to Intel Offload into. I would like to transfer immediately…
JudgeDeath
  • 151
  • 1
  • 2
  • 9
1
vote
2 answers

Confusion about compiling with AVX512

I'm reading this document about how to compile C/C++ code using the Intel C++ compiler and AVX512 support on a Intel Knights Landing. However, I'm a little bit confused about this part: -xMIC-AVX512: use this option to generate AVX-512F, AVX-512CD,…
justHelloWorld
  • 6,478
  • 8
  • 58
  • 138
1 2 3
…
12 13