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I'm using DIGILENT's Atlys FPGA board for image processing but i'm facing one problem that is when i do software co simulation using Black box i'm getting the output very soon i.e, within 1 min but when i generate hardware co simulation model and use for hardware co simulation the output i'm getting taking very long time 20 to 30 mins. why is this? and how to overcome this long time?

FPGA LORD
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    Do those 20 mins contain the build time? – mbschenkel Feb 21 '14 at 16:59
  • No i'm using simulink model and xilinx system generator...for the interfacing pc to fpga using jtag connection... – FPGA LORD Feb 22 '14 at 11:12
  • Do you mean that for the FPGA-in-the-loop setup you are feeding in the input-data (images in your case) over JTAG? Could you show or explain how that is done? Also, what is behind the "software co simulation"? Just Simulink or Simulink + ModelSim or ...? – mbschenkel Feb 22 '14 at 17:11
  • yaa..for software Simulink+ISE simulator i'm using...getting the output within 1 min but in hardware in the loop its taking lot of time... i got it why its taking 20 min but trying to solve it.. – FPGA LORD Feb 23 '14 at 07:55

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