I use code VHDL to make a one-shot timer in Simulink by "black box" of System Generator. The module concludes input is: clk, en, trigger, delay & output is: pluse. Now I want to use System Generator to implement on Zynq 7020 and use clock frequency = 1.562Mhz. I read "ug897-vivado-system generator-user", but i still dont know how to configure clk.
The diagram in Matlab/Simulink
The VHDL code for one-shot timer/black box
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity oneshot is
port ( clk : in STD_LOGIC;
ce : in STD_LOGIC;
trigger : in STD_LOGIC:='0';
delay : in STD_LOGIC_VECTOR (7 downto 0);
pulse : out STD_LOGIC :='0');
end oneshot;
architecture Behavioral of oneshot is
signal count: INTEGER range 0 to 255; -- count variable
signal bus_rising_edge : boolean;
signal input_sync : std_logic_vector(0 to 2);
begin
input_syncronizer : process(clk) begin
if rising_edge(clk) then
input_sync <= to_x01(trigger)&input_sync(0 to 1);
end if;
end process ;
bus_rising_edge <= input_sync(0 to 1) = "10";
trigger_process: process (clk)
begin
-- wait for trigger leading edge
if rising_edge(clk) then
if bus_rising_edge then
pulse <= '1';
count <= to_integer(unsigned(delay));
elsif count > 1 then
pulse <= '1';
count <= count - 1;
else
pulse <= '0';
end if;
end if;
end process;
end Behavioral;
The Matlab code automatically create when importing VHDL code https://drive.google.com/open?id=1jfztL-NgftDc7VAgAX4eHfuJF8uOgK3V
(sorry i cant post my code properly)
