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Questions tagged [riscv]

For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use. Note: Questions on hardware implementation will be more appropriate for the electronics engineering site: https://electronics.stackexchange.com

Summary

RISC-V (pronounced "risk-five") is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Features

  • A completely open ISA that is freely available to academia and industry.

  • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.

  • An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, and FPGA), but which allows efficient implementation in any of these.

  • An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

  • Support for the revised 2008 IEEE-754 floating-point standard.

  • An ISA supporting extensive user-level ISA extensions and specialized variants.

  • 32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.

  • An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.

  • A fully virtualizable ISA to ease hypervisor development.

  • An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

References

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RISC-V interrupts, setting up MTIMECMP

I am trying to write a program in RISC-V assembly for HiFive1 board to wake up with timer interrupt This is my interrupt setup routine .section .text .align 2 .globl setupINTERRUPT .equ MTIMECMP, 0x2004000 setupINTERRUPT: addi sp, sp, -16 …
Ivan
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RISC-V exceptions vs interrupts

I am about to write my own RV32I core with a CLINT. However there is something which is not fully clear to me. At least I could not find it in the docs. Here is what the privileged isa spec says for ecall/ebreak: ECALL and EBREAK cause the…
developer123
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How to add custom instruction to RISCV cross compiler?

I cloned riscv-tools (https://github.com/riscv/riscv-tools) and riscv-gnu-toolchain ( https://github.com/riscv/riscv-gnu-toolchain) and was able to get Spike, pk, and the cross compiler (riscv64-unknown-elf-gcc) to work. I want to extend this and be…
mr_broccoli
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RISC-V SiFive HiFive Unleashed FMADD(32) underflow flag not setting on subnormal result

so my issue is either out of my understanding of fpu mechanics, or there is a problem with implementation I am using. Issue: When performing fused multiply-add instruction with source operand values as such, rs1 = 0xBF800000, rs2 = 0x80542353, rs3 =…
Mateusz Kowalski
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Rotating bits in RISC-V

Hey so I am kinda new here and to RISC-V. One of my exercise questions is: Rotate right by 4 bits the value of 0x0000000000000123. The expected result is 0x3000000000000012, i.e. all hexadecimal digits move right by one position while the rightmost…
amiteur
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RISC-V generate -1 / 0xFFFFFFFF in a register with LUI / ADDI?

I am learning how to write code for a RISC-V processor. I want to store a value of 0xFFFFFFFF into memory / a register. I can extend the 12 immediate bits of addi instruction by adding a lui before it, something like this: lui t0, 0xFFFFF addi t0,…
Kralik_011
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How to represent the product of multiplication instructions in RISCV?

In RISCV, we have mul t1, s1, s2 and mulh t2, s1, s2 instructions, which store the lower 32-bits of the product and upper 32-bits of the product respectively. If I need to use the product, should I do add t0, t2, t1? Thank you!
Natarich J
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How does RISC-V variable length of instruction work in detail?

After skimming the RISC-V ISA doc, it gives me the impression that the RISC-V supports both 16-bit(RVC), 32-bit(RV32I), and 64-bit(RV64I) length of instructions. For the RV32I: immediate is signed extended to 32 bits Instruction length:32…
Billy
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LLVM Instruction Scheduling in RISC-V

I am looking at instruction scheduling in LLVM for RISC-V backend. I understood there are two ways of scheduling (ScheduleDAGRRList & MachineScheduler). From debug logs i can RISC-V uses ScheduleDAGRRList approach. Is MachineScheduler is better…
harry
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Who provides syscalls in qemu-riscv?

I started learn riscv. I got qemu-riscv, riscv-gcc and compiled next hello world asm program: .section .text .globl _start _start: li a0, 0 # stdout 1: auipc a1, %pcrel_hi(msg) # load msg(hi) addi a1, a1,…
dimcha
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GDB on RISC-V QEMU

We are porting OpenJDK to RISC-V. We're at the point that the interpreter builds. We need to debug it, using GDB. However, we haven't been able to find a working GDB that works with RISC-V QEMU. Any help would be much appreciated.
seanhalle
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Why does RV32I include instructions like ADDI and XORI but not BLTI?

I'm not experienced in ISA design. I've been reading https://riscv.org/specifications/ chapter 2, page 21. Could someone explain why RISC-V has arithmetic and logical instructions which use immediates, such as ADDI and XORI, but not similar…
fadedbee
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What is the minimum RISC-V instruction set that runs GNU/Linux?

I want to build my own minimal RISC-V processor for a FPGA. The processor will as simple as possible with only one pipeline. I read the entire RISC-V ISA and there are many standard extensions. So what is the minimum RISC-V ISA that can run linux?
ArchHaskeller
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Why doesn't the GCC assembly output generate a .GLOBAL for printf

I have a trivial example C program:- #include int main() { printf("hello world!"); return 1; } I use the following command to compile it and generate assembly:- riscv32-unknown-elf-gcc -S hello.c -o hello.asm Which generates the…
Phil Wright
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Chisel -- clock gating

Clock gating is important for power reduction. How do we specify clock gating in Chisel? Clock gating is where a logic signal determines whether or not the clock to a particular register is toggled. When the logic signal is inactive, then the…
seanhalle
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