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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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What is I/O Area and Memory area in pci driver WEC7

I hear the terms I/O area and Memory Area frequently from teammates in my project( PCIe Gigabit ethernet driver development in WEC7) . I have no idea about it . Please knowledge me about it .
skanda93
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PCIe message reception on RC causing unhandled signal 11

I am using a powerpc processor booting with u-boot and running kernel 3.18, with 1G DDR RAM. I configure a PCIe inbound window with u-boot from address 0x3FE00000 to 0x3FE200000(DDR goes from address 0x00000000 to 0x40000000). Then, I boot the…
martrab
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Failed to enable MSI-X interrupt in Linux System

I am working on PCIe based Cyclone V FPGA board in Linux Platform. I have tried with legacy interrupt which works fine in my PCIe Driver. Now, I want to enable MSI-X interrupt in my PCIe driver. MSI-X interrupt is implemented in FPGA system and I am…
Ritesh Prajapati
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PCI Root Complex BAR usage

I want to understand the usage of BARs in the PCIe Root Complex. The PCIe Root Complex is already a part of the CPU (as a peripheral to it). And the CPU register spaces is easily accessible. CPU has register to access its various peripheral link…
user5372659
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Can 1 CPU access another's PCI resources

We are developing a CUDA-based system for a large statistical analysis. I have a dual-socket motherboard, where each socket is assigned different PCI slots. 2x x16, 1 x8 for each LGA 2011 CPU (i.e. 40 lanes each). My question is: Can 1 CPU access…
Sheldon Ross
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TechWell TW6869 driver does not generate interrupts on embedded device

I'm trying to get a Techwell TW6869 driver to work. This PCIe-chip is able to capture analog video signals. Therefore I'm using a driver which can be found here: GitHub The chip is connected to a Freescale imx.6 processor which is running Angström…
user2035598
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Pci express - communicate kernel -> graphic card

The final goal is to be able to write to a PCIE device from the kernel, without the already made functions, to understand the inner working (and then, obviously, use them again). I saw the PCIE specs which are 800+ pages (the 3.0 especially). Huge…
Kroma
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Are PCIe device drivers beneficial if using Linux as a bootloader for bare-metal code?

I am developing an embedded system on a PowerPC processor and there is need for communication with an FPGA via PCIe. I wish to use Linux/embedded-Linux as a bootloader to leverage its PCIe initialization code and driver API for simplified PCIe…
Tyler
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Is it possible to use dma_set_mask() to tell kernel not to use memory under 4G

My pcie device has a bug that it cant dma to addresses below 4G, What mask should i use with dma_set_mask to tell this to the kernel?
yonigo
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Use dma transfert with Cyclone V Avalon-MM for PCIe

Is it possible to do DMA transferts with the IP core «Cyclone V Avalon-MM for PCIe» provided by altera in Qsys (quartus 14.0) ? Altera provide an ip-core named «Cyclone V Avalon-MM DMA for PCIe» to do dma transfert. But this ip-core does not support…
FabienM
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How to get a PCIE device's link speed on Windows 7/8 programmatically

On Windows 8 when I right click on a PCIE device in Device Manager, in the Details tab, under property "PCI current link speed" I can read the PCIe link speed. The same can be done for the PCIe link width. I'd like to access this information…
Phy2Dig
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Regarding usage of write system call on a device node

I am having problem understanding difference between below two code cases. Case 1 is working as per expectation and Case 2 is not. Problem Statement: I need to write some set of DWORDS on my device file and trigger a DMA. DMA capacity is 128*4…
bdubey
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How program for graceful removal/or no removal if device node is in use

I have this device node created using mknod command for a pcie driver. /dev/pciedrv Upon removing the driver while device node file is open (in use), the system crashes. rmmod -f pciedrv Is there a way to do a graceful exit? Also how to handle the…
bdubey
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How long does it take to set up an I/O controller on PCIe bus

Say I have an InfiniBand or similar PCIe device and a fast Intel Core CPU and I want to send e.g. 8 bytes of user data over the IB link. Say also that there is no device driver or other kernel: we're keeping this simple and just writing directly to…
rivimey
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pci_disable_msi Oops Bug

I am trying to write a kernel module that will handle MSI interrupts for a PCIe device. I have written a simple skeleton outline for my driver currently and whenever I try to call 'pci_disable_msi(dev)' I get an unable to handle kernel NULL pointer…
whh4000
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